Handbook of algorithms for physical design automation part 2

x Chapter 32 Chapter 33 Chapter 34 Contents Optimization Techniques in Routing ................................................ 627 Christoph Albrecht Global Interconnect Planning........................................................ 645 Cheng-Kok Koh, Evangeline F.Y. Young, and Yao-Wen Chang Coupling Noise ....................................................................... 673 Rajendran Panda, Vladimir Zolotov, and Murat Becer PART VII Manufacturability and Detailed Routing Chapter 35 Chapter 36 Chapter 37 Chapter 38 Modeling and Computational Lithography ......................................... 695 Franklin M. Schellenberg CMP Fill Synthesis: A Survey of Recent Studies................................... 737 Andrew B. Kahng and Kambiz Samadi Yield Analysis and Optimization .................................................... 771 Puneet Gupta and Evanthia Papadopoulou Manufacturability-AwareRouting................................................... 791 Minsik Cho, Joydeep Mitra, and David Z. Pan PART VIII Physical Synthesis Chapter 39 Chapter 40 Placement-Driven Synthesis Design Closure Tool.................................. 813 Charles J. Alpert, Nathaniel Hieter, Arjen Mets, Ruchir Puri, Lakshmi Reddy, Haoxing Ren, and Louise Trevillyan X Architecture Place and Route: Physical Design for the X Interconnect Architecture .......................................................................... 835 Steve Teig, Asmus Hetzel, Joseph Ganley, Jon Frankle, and Aki Fujimura PART IX Chapter 41 Designing Large Global Nets Inductance Effects in Global Nets ................................................... 865 Yehea I. Ismail Contents Chapter 42 Chapter 43 Chapter 44 PART X Chapter 45 Chapter 46 Chapter 47 xi Clock Network Design: Basics ...................................................... 881 Chris Chu and Min Pan Practical Issues in Clock Network Design .......................................... 897 Chris Chu and Min Pan Power Grid Design ................................................................... 913 Haihua Su and Sani Nassif Physical Design for Specialized Technologies Field-Programmable Gate Array Architectures..................................... 941 Steven J.E. Wilton, Nathalie Chan King Choy, Scott Y.L. Chin, and Kara K.W. Poon FPGA Technology Mapping, Placement, and Routing ............................. 957 Kia Bazargan Physical Design for Three-Dimensional Circuits ................................... 985 Kia Bazargan and Sachin S. Sapatnekar Index.................................................................................................1003 Editors CharlesJ.Alpert (Chuck)wasborninBethesda,Maryland,in1969.Hereceivedtwoundergraduate degrees from Stanford University in 1991 and his doctorate from the University of California, Los Angeles, California in 1996, in computer science. Upon graduation, Chuck joined IBM’s Austin Research Laboratory where he currently manages the Design Productivity Group, whose mission is to develop design automation tools and methodologiesto improve designer productivityand reduce design cost. Chuck has over 100 conference and journal publications and has thrice received the best paper award from the ACM/IEEE Design Automation Conference. He has been active in the academic community,serving as chair for the Tau Workshop on Timing Issues and the International Symposium on Physical Design. He also serves as an associate editor of IEEE Transactions on Computer-Aided Design. He received the Mahboob Khan Mentor Award in 2001 and 2007 for his work in mentoring. He was also named the IEEE fellow in 2005. DineshP.MehtareceivedhisBTechincomputerscienceandengineeringfromtheIndianInstituteof Technology,Bombay,India, in 1987;his MS in computerscience fromthe Universityof Minnesota, Minneapolis, Minnesota, in 1990; and his PhD in computer science from the University of Florida, Gainesville, Florida, in 1992. He was on the faculty at the University of Tennessee Space Institute, Tullahoma,Tennesseefrom1992to2000,wherehereceivedtheVicePresident’sAwardforTeaching Excellence in 1997. He was a visiting professor at Intel’s Strategic CAD Labs in 1996 and 1997. He has been on the faculty in the mathematical and computer science departments at the Colorado School of Mines, Golden, Colorado since 2000, where he is a professor and currently also serves as department head. He is a coauthor of Fundamentals of Data Structures in C++ and a coeditor of Handbook of Data Structures and Applications. His publications and research interests are in VLSI design automation,and applied algorithms and data structures. He is a formerassociate editor of the IEEE Transactions on Circuits and Systems-I. Sachin S. Sapatnekar received his BTech from the Indian Institute of Technology, Bombay, India in 1987; his MS from Syracuse University, New York, in 1989; and his PhD from the University of Illinois at Urbana–Champaign, Urbana, Illinois, in 1992. From 1992 to 1997, he was an assistant professorintheDepartmentofElectricalandComputerEngineeringatIowaStateUniversity,Ames, Iowa. Since then, he has been on the faculty of the Department of Electrical and Computer Engi-neering at the University of Minnesota, Minneapolis, Minnesota, where he is currently the Robert and Marjorie Henle Professor. He has published widely in the area of computer-aided design of VLSI circuits, particularly in the areas of timing, layout, and power. He has held positions on the editorial board of the IEEE Transactions on CAD (he is currently the deputy editor-in-chief), the IEEE Transactions on VLSI Systems, and the IEEE Transactions on Circuits and Systems II. He has served on the technical programcommittee for various conferences,as a technical programco-chair for Design Automation Conference (DAC), and as a technical program and general chair for both the IEEE/ACM Tau Workshop and the ACM International Symposium on Physical Design. He is a recipient of the NSF Career Award, three best paper awards at DAC, and one at International Conference on Computer Design (ICCD), and the Semiconductor Research Corporation Technical Excellence award. He is a fellow of the IEEE. xiii ... - tailieumienphi.vn