Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm
Optimization of a novel programmable data-flow crypto processor using NSGA-II algorithm
The optimization of a novel programmable data-flow crypto processor dedicated to security applications is considered. An architecture based on assigning basic functional units to four synchronous regions was proposed in a previous work. In this paper, the problem of selecting the number of synchronous regions and the distribution of functional units among these regions is formulated as a combinatorial multi-objective optimization problem. The objective functions are chosen as: the implementation