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dce 2013
COMPUTER CSE
ARCHITECTURE Fall 2013
BK
TP.HCM
Faculty of Computer Science and Engineering
Department of Computer Engineering
Vo Tan Phuong http://www.cse.hcmut.edu.vn/~vtphuong
dce 2013
Chapter 5 Memory
Computer Architecture – Chapter 5 ©Fall 2013, CS 2
dce 2013
Presentation Outline
Random Access Memory and its Structure
Memory Hierarchy and the need for Cache Memory
The Basics of Caches
Cache Performance and Memory Stall Cycles
Improving Cache Performance
Multilevel Caches
Computer Architecture – Chapter 5 ©Fall 2013, CS 3
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Random Access Memory
Large arrays of storage cells
Volatile memory
Hold the stored data as long as it is powered on
Random Access
Access time is practically the same to any data on a RAM chip
Output Enable (OE) control signal
Specifies read operation
n RAM Address
Write Enable (WE) control signal
Specifies write operation
Data m
OE WE
2n × m RAM chip: n-bit address and m-bit data
Computer Architecture – Chapter 5 ©Fall 2013, CS 4
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Memory Technology
Static RAM (SRAM) for Cache Requires 6 transistors per bit Requires low power to retain bit
Dynamic RAM (DRAM) for Main Memory One transistor + capacitor per bit
Must be re-written after being read Must also be periodically refreshed
Each row can be refreshed simultaneously Address lines are multiplexed
Upper half of address:
Lower half of address:
Row Access Strobe (RAS)
Column Access Strobe (CAS)
Computer Architecture – Chapter 5 ©Fall 2013, CS 5
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