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Computer Architecture
Chapter 8 Multiprocessors
Shared Memory Architectures
Prof. Jerry Breecher CSCI 240 Fall 2003
Chapter Overview
We’re going to do only one section from this chapter, that part related to how caches from multiple processors interact with each other.
8.1 Introduction – the big picture
8.3 Centralized Shared Memory Architectures
Chap. 8 Multiprocessors 2
Introduction
The Big Picture: Where are We Now?
8.1 Introduction
8.3 Centralized Shared Memory Architectures
The major issue is this:
We’ve taken copies of the contents of main memory and put them in caches closer to the processors. But what happens to those copies if someone else wants to use the main memory data?
How do we keep all copies of the data in synch with each other?
Chap. 8 Multiprocessors 3
The Multiprocessor Picture
Processor/Memory Bus
Example: Pentium System Organization
PCI Bus
I/O Busses
Chap. 8 Multiprocessors 4
Shared Memory Multiprocessor
Processor
Registers
Caches
Processor
Registers
Caches
Processor
Registers
Caches
Processor
Registers
Caches
Memory
Disk & other IO
Chipset •Memory: centralized with Uniform Memory Access time (“uma”) and bus interconnect, I/O
•Examples: Sun Enterprise 6000, SGI Challenge, Intel SystemPro
Chap. 8 Multiprocessors 5
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