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Computer Architecture
Chapter 2 Instruction Sets
Prof. Jerry Breecher CSCI 240 Fall 2003
Introduction
2.1 Introduction
2.2 Classifying Instruction Set Architectures 2.3 Memory Addressing
2.4 Operations in the Instruction Set 2.5 Type and Size of Operands
2.6 Encoding and Instruction Set 2.7 The Role of Compilers
2.8 The MIPS Architecture Bonus
Chap. 2 Instruction Sets 2
Introduction
The Instruction Set Architecture is that portion of the machine visible to the assembly level programmer or to the compiler writer.
software
instruction set
hardware
1. What are the advantages and disadvantages of various instruction set alternatives.
2. How do languages and compilers affect ISA.
3. Use the DLX architecture as an example of a RISC architecture.
Chap. 2 Instruction Sets 3
Classifying Instruction Set
2.1 Introduction
2.2 Classifying Instruction Set Architectures
2.3 Memory Addressing
2.4 Operations in the Instruction Set
2.5 Type and Size of Operands
Architectures
Classifications can be by:
2.6 Encoding and Instruction Set
2.7 The Role of Compilers
2.8 The DLX Architecture
1. Stack/accumulator/register
2. Number of memory operands.
3. Number of total operands.
Chap. 2 Instruction Sets 4
Instruction Set Basic ISA Architectures Classes
Accumulator:
1 address add A 1+x address addx A
Stack:
0 address add
General Purpose Register:
2 address add A B
3 address add A B C
acc acc + mem[A] acc acc + mem[A + x]
tos tos + next
EA(A) EA(A) + EA(B)
EA(A) EA(B) + EA(C)
ALU Instructions can have two or three operands.
Load/Store:
0 Memory
load R1, Mem1 load R2, Mem2
add R1, R2
ALU Instructions can have 0, 1, 2, 3 operands. Shown here are cases of 0 and 1.
1 Memory add R1, Mem2
Chap. 2 Instruction Sets 5
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