Ebook MSP430x4xx Family

MSP430x4xx Family User’s Guide April 2013 SLAU056L Related Documentation From Texas Instruments Preface Read This First About This Manual This manual discusses modules and peripherals of the MSP430x4xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family. Pin functions, internal signal connections and operational parameters differ from device to device. The user should consult the device-specific data sheet for these details. Related Documentation From Texas Instruments For related documentation see the web site http://www.ti.com/msp430. FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Notational Conventions Program examples, are shown in a special typeface. iii Glossary Glossary ACLK ADC BOR BSL CPU DAC DCO dst FLL GIE INT(N/2) I/O ISR LSB LSD LPM MAB MCLK MDB MSB MSD NMI PC POR PUC RAM SCG SFR SMCLK SP SR src TOS WDT Auxiliary Clock Analog-to-Digital Converter Brown-Out Reset Bootstrap Loader Central Processing Unit Digital-to-Analog Converter Digitally Controlled Oscillator Destination Frequency Locked Loop General Interrupt Enable Integer portion of N/2 Input/Output Interrupt Service Routine Least-Significant Bit Least-Significant Digit Low-Power Mode Memory Address Bus Master Clock Memory Data Bus Most-Significant Bit Most-Significant Digit (Non)-Maskable Interrupt Program Counter Power-On Reset Power-Up Clear Random Access Memory System Clock Generator Special Function Register Sub-System Master Clock Stack Pointer Status Register Source Top-of-Stack Watchdog Timer See Basic Clock Module See System Resets, Interrupts, and Operating Modes See www.ti.com/msp430 for application reports See RISC 16-Bit CPU See FLL+ Module See RISC 16-Bit CPU See FLL+ Module See System Resets Interrupts and Operating Modes See Digital I/O See System Resets Interrupts and Operating Modes See FLL+ Module See System Resets Interrupts and Operating Modes See RISC 16-Bit CPU See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See FLL+ Module See RISC 16-Bit CPU See RISC 16-Bit CPU See RISC 16-Bit CPU See RISC 16-Bit CPU See Watchdog Timer iv Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition: Register Bit Accessibility and Initial Condition Key rw r r0 r1 w w0 w1 (w) h0 h1 −0,−1 −(0),−(1) Bit Accessibility Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. Cleared by hardware Set by hardware Condition after PUC Condition after POR v ... - tailieumienphi.vn