Synthesis is the process by which you convert a design written at the register-transfer level (RTL) into a gate-level netlist. The RTL specification is written in Verilog or VHDL, using high-level constructs such as for loops and case statements. The synthesis tool transforms this RTL specification into a set of logic gates,such as AND, OR, and BUF, that are connected in a network. To specify the gates that the synthesis tool uses to build a netlist, you need to choose a technology from a specif