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Ebook Engineering circuit analysis (8th edition): Part 1
(BQ) Part 1 book Engineering circuit analysis has contents: Basic components and electric circuits, voltage and current laws, basic nodal and mesh analysis, handy circuit analysis techniques, the operational amplifier, capacitors and inductors, basic RL and RC circuits, the RLC circuit,...and other content.
8/30/2018 5:29:34 AM +00:00
Ebook Engineering circuit analysis (8th edition): Part 2
(BQ) Part 2 book Engineering circuit analysis has contents: AC circuit power analysis, polyphase circuits, magnetically coupled circuits, complex frequency and the laplace transform, circuit analysis in the s-domain, frequency response, two-port networks,...and other content.
8/30/2018 5:29:34 AM +00:00
Ebook 3G Evolution: HSPA and LTE for mobile broadband: Part 1
(BQ) Part 1 book 3G Evolution: HSPA and LTE for mobile broadband has contents: Background of 3G evolution, background of 3G evolution, high data rates in mobile communication, OFDM transmission, wider-band ‘single-carrier’ transmission, multi-antenna techniques,... and other contents.
8/30/2018 5:29:27 AM +00:00
Ebook 3G Evolution: HSPA and LTE for mobile broadband: Part 2
(BQ) Part 2 book 3G Evolution: HSPA and LTE for mobile broadband has contents: Enhanced uplink, MBMS - multimedia broadcast multicast services, HSPA evolution, LTE and SAE - introduction and design targets, LTE radio access - An overview... and other contents.
8/30/2018 5:29:27 AM +00:00
Bài giảng môn DSP - Chương 2: Biểu diễn hệ thống và tín hiệu rời rạc trong miền Z
Bài giảng có nội dung trình bày: định nghĩa Biến đổi Z hai phía và một phía, sự tồn tại của biến đổi Z và cực và không (Poles and Zeros. Để biết rõ hơn về nội dung chi tiết, mời các bạn cùng tham khảo.
8/30/2018 5:29:22 AM +00:00
Bài giảng Bộ biến đổi số - tương tự (DAC)
DAC hay Mạch chuyển đổi số ra tương tự, hay Digital-to-analog converter, là một Linh kiện bán dẫn thực hiện chuyển đổi dữ liệu kỹ thuật số (thường là nhị phân) thành tín hiệu tương tự thường là điện áp.
8/30/2018 5:29:22 AM +00:00
Bài thuyết trình Bảo vệ đường dây
Bài thuyết trình Bảo vệ đường dây trình bày nội dung về các sơ đồ bảo vệ đường dây, như các sơ đồ pilot không toàn phần, các sơ đồ pilot bảo vệ toàn phần,.... Để biết rõ hơn về nội dung chi tiết, mời các bạn cùng tham khảo.
8/30/2018 5:28:07 AM +00:00
Tối ưu hóa các cơ hội tăng trưởng cho Viễn thông Việt Nam
Với chủ đề Tối ưu hóa các cơ hội tăng trưởng cho Viễn thông Việt Nam, Hội nghị Tăng trưởng Viễn thông Việt Nam 2009 đã diễn ra trong hai ngày 23 và 24/9/2009 tại Hà Nội do Viện Chiến lược TT&TT (Bộ TT&TT) và Frost & Sullivan tổ chức. Hội nghị đã tập trung trình bày các khía cạnh giúp ngành Viễn thông tăng trưởng từ các cơ hội, mô hình kinh doanh mới cho các nhà cung cấp dịch vụ viễn thông, làm thế nào để 3G vận hành?
8/30/2018 5:27:52 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 1, 2 - Keshab K. Parhi
Chapter 1, 2 introduction to DSP Systems and iteration bound. The main contents of this chapter include all of the following: Typical DSP programs, loop bound, iteration bound.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 3 - Keshab K. Parhi
In this chapter discuss the pipelining and parallel processing. The main contents of this chapter include all of the following: Pipelining of FIR digital filters, parallel processing, pipelining and parallel processing for low power.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 4 - Keshab K. Parhi
Lecture VLSI Digital signal processing systems - Chapter 4 introduce the retiming. The main contents of this chapter include: Retiming formulation, properties of retiming, cutset retiming,...and another content.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 5 - Keshab K. Parhi
Lecture VLSI Digital signal processing systems - Chapter 5 discuss the unfolding. The main contents of this chapter include: Algorithm for unfolding, applications of unfolding, sample period reduction, parallel processing,... Inviting you refer.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 6 - Keshab K. Parhi
Folding is a technique to reduce the silicon area by timemultiplexing many algorithm operations into single functional units (such as adders and multipliers). Chapter 6 will discuss the folding, inviting you refer.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 7 - Keshab K. Parhi
Systolic architectures are designed by using linear mapping techniques on regular dependence graphs (DG). Systolic architectures have a space-time representation where each node is mapped to a certain processing element (PE) and is scheduled at a particular time instance. Chapter 7 will discuss the systolic architecture design, inviting you refer.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 8 - Keshab K. Parhi
The main contents of this chapter include all of the following: Cook-toom algorithm and modified cook-toom algorithm, winograd algorithm and modified winograd algorithm, iterated convolution, cyclic convolution, design of fast convolution algorithm by inspection.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 9 - Keshab K. Parhi
Strength reduction leads to a reduction in hardware complexity by exploiting substructure sharing and leads to less silicon area or power consumption in a VLSI ASIC implementation or less iteration period in a programmable DSP implementation. Strength reduction enables design of parallel FIR filters with a lessthan-linear increase in hardware.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 10 - Keshab K. Parhi
Chapter 10 introduce the pipelined and parallel pecursive and adaptive filters. This chapter includes content: Pipelining in 1st-Order IIR Digital Filters, Pipelining in Higher-Order IIR Digital Filters, Parallel Processing for IIR Filters, Combined Pipelining and Parallel Processing for IIR Filters.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 11 - Keshab K. Parhi
Chapter 11 - Scaling and round-off noise includes content: Scaling and round-off noise; state variable description of digital filters; scaling and round-off noise computation; round-off noise computation using state variable description; slow-down, retiming, and pipelining.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 13 - Keshab K. Parhi
Chapter 13 - Bit level arithmetic architectures. This chapter includes content: Parallel multipliers, parallel multiplication with sign extension, baugh-wooley multipliers, parallel multipliers with modified booth recoding, interleaved floor-plan and bit-plane-based digital filters, design of bit-serial multipliers using systolic mappings,...
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 14 - Keshab K. Parhi
Chapter 14 includes content: Redundant number representations, hybrid radix-2 addition, hybrid radix-2 subtraction, hybrid radix-2 addition/subtraction, signed binary digit (SBD) addition/subtraction, maximally redundant hybrid radix-4 addition,...
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 15, 16 - Keshab K. Parhi
Lecture VLSI Digital signal processing systems, chapter 15, 16 includes contents: Multiple constant multiplication (MCM), linear transformations, polynomial evaluation, sub-expression sharing in digital filters, using 2 most common sub-expressions in CSD representation.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 17 - Keshab K. Parhi
Lecture VLSI Digital signal processing systems - Chapter 17: Low-power design includes content as: VLSI digital signal processing systems, power consumption in DSP, power dissipation, CMOS power consumption, dynamic power consumption, switching activity (α), increased switching activity due to glitching,…
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 18 - Keshab K. Parhi
Lecture VLSI Digital signal processing systems: Chapter 18 includes the following content: DSP applications, DSP features, addressing modes, standard DSP alternatives, architectural partitioning,... Inviting you refer.
8/30/2018 5:27:46 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 1, 2 - Keshab K. Parhi
Chapter 1, 2 introduction to DSP Systems and iteration bound. The main contents of this chapter include all of the following: Typical DSP programs, loop bound, iteration bound.
8/30/2018 5:27:34 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 3 - Keshab K. Parhi
In this chapter discuss the pipelining and parallel processing. The main contents of this chapter include all of the following: Pipelining of FIR digital filters, parallel processing, pipelining and parallel processing for low power.
8/30/2018 5:27:34 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 4 - Keshab K. Parhi
Lecture VLSI Digital signal processing systems - Chapter 4 introduce the retiming. The main contents of this chapter include: Retiming formulation, properties of retiming, cutset retiming,...and another content.
8/30/2018 5:27:34 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 5 - Keshab K. Parhi
Lecture VLSI Digital signal processing systems - Chapter 5 discuss the unfolding. The main contents of this chapter include: Algorithm for unfolding, applications of unfolding, sample period reduction, parallel processing,... Inviting you refer.
8/30/2018 5:27:34 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 6 - Keshab K. Parhi
Folding is a technique to reduce the silicon area by timemultiplexing many algorithm operations into single functional units (such as adders and multipliers). Chapter 6 will discuss the folding, inviting you refer.
8/30/2018 5:27:34 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 7 - Keshab K. Parhi
Systolic architectures are designed by using linear mapping techniques on regular dependence graphs (DG). Systolic architectures have a space-time representation where each node is mapped to a certain processing element (PE) and is scheduled at a particular time instance. Chapter 7 will discuss the systolic architecture design, inviting you refer.
8/30/2018 5:27:34 AM +00:00
Lecture VLSI Digital signal processing systems: Chapter 8 - Keshab K. Parhi
The main contents of this chapter include all of the following: Cook-toom algorithm and modified cook-toom algorithm, winograd algorithm and modified winograd algorithm, iterated convolution, cyclic convolution, design of fast convolution algorithm by inspection.
8/30/2018 5:27:34 AM +00:00