Solutions for CMOS VLSI Design 4th Edition (Odd).

Solutions Solutions for CMOS VLSI Design 4th Edition. Last updated 12 May 2010. Chapter 1 1.1 Starting with 100,000,000 transistors in 2004 and doubling every 26 months for 12 ⎛----------------⎞ years gives 10 • 2 ≈ 4.6B transistors. 1.3 Let your imagination soar! 1.5 A B C D Y 1.7 A Y (a) A Y (b) B A A Y B (c) B C Y (d) 1 2 SOLUTIONS 1.9 A1A1A0A0 Y0 Y1 A0 A1 Y0 A2 Y2 A1 Y3 Y1 A0 (a) (b) 1.11 The minimum area is 5 tracks by 5 tracks (40 λ x 40 λ = 1600 λ2). 1.13 B A GND Y VDD n+ n+ n+ p+ p+ p substrate n well 1.15 This latch is nearly identical save that the inverter and transmission gate feedback CHAPTER 2 SOLUTIONS 3 has been replaced by a tristate feedaback gate. CLK D Y CLK CLK CLK 1.17 VDD A B C D A D B C F F C D A B GND (a) (b) (c) 5 x 6 tracks = 40 λ x 48 λ = 1920 λ2. (with a bit of care) (d-e) The layout should be similar to the stick diagram. 1.19 20 transistors, vs. 10 in 1.16(a). A B A C B C Y 1.21 The Electric lab solutions are available to instructors on the web. The Cadence labs include walking you through the steps. Chapter 2 4 SOLUTIONS 2.1 W ⎛3.9•8.85⋅10−14 ⎞⎛W ⎞ W 2 ox L ⎝ 100⋅10−8 ⎠⎝ L ⎠ L 2.5 Vgs = 5 2 1.5 Vgs = 4 1 Vgs = 3 0.5 00 1 2 Vgs = 2 Vgs = 1 3 4 5 Vds 2.3 The body effect does not change (a) because Vsb = 0. The body effect raises the threshold of the top transistor in (b) because Vsb > 0. This lowers the current through the series transistors, so IDS1 > IDS2. 2.5 The minimum size diffusion contact is 4 x 5 λ, or 1.2 x 1.5 μm. The area is 1.8 μm2 and perimeter is 5.4 μm. Hence the total capacitance is Cdb(0V) = (1.8)(0.42) + (5.4)(0.33) = 2.54fF At a drain voltage of VDD, the capacitance reduces to Cdb(5V) = (1.8)(0.42)⎛1 + ----------⎞–0.44 + (5.4)(0.33)⎛1 + ----------⎞–0.12 = 1.78fF 2.7 The new threshold voltage is found as 17 φs = 2(0.026)ln1.45•1010 = 0.85V γ = 3.9•8.85•10−14 2(1.6•10−19 )(11.7•8.85•10−14 )(2•1017 )= 0.75V1/2 V = 0.7+γ φs +4 − φs =1.66V The threshold increases by 0.96 V. CHAPTER 3 SOLUTIONS 5 2.9 The threshold is increased by applying a negative body voltage so Vsb > 0. 2.11 The nMOS will be OFF and will see Vds = VDD, so its leakage is −V Ileak = Idsn = βvTe1.8envT = 69pA 2.13 Assume VDD = 1.8 V. For a single transistor with n = 1.4, −Vt +ηVDD Ileak = Idsn = βvTe1.8e nvT = 499pA For two transistors in series, the intermediate voltage x and leakage current are found as: −Vt +ηx −x η(VDD −x)−V −x 2 1.8 nvT vT 2 1.8 nvT leak T ⎝ ⎠ T −Vt +ηx −x η(VDD −x)−V −x e nvT ⎜1−evT ⎟ = e nvT ⎝ ⎠ x = 69 mV; Ileak = 69 pA In summary, accounting for DIBL leads to more overall leakage in both cases. However, the leakage through series transistors is much less than half of that through a single transistor because the bottom transistor sees a small Vds and much less DIBL. This is called the stack effect. For n = 1.0, the leakage currents through a single transistor and pair of transistors are 13.5 pA and 0.9 pA, respectively. 2.15 VIL = 0.3; VIH = 1.05; VOL = 0.15; VOH = 1.2; NMH = 0.15; NML = 0.15 2.17 Either take the grungy derivative for the unity gain point or solve numerically for VIL = 0.46 V, VIH = 0.54 V, VOL = 0.04 V, VOH = 0.96 V, NMH = NML = 0.42 V. 2.19 Take derivatives or solve numerically for the unity gain points: VIL = 0.43 V, VIH = 0.50 V, VOL = 0.04 V, VOH = 0.97 V, NMH = 0.39, NML = 0.47 V. 2.21 (a) 0; (b) 0.6; (c) 0.8; (d) 0.8 Chapter 3 3.1 First, the cost per wafer for each step and scan. 248nm – number of wafers for four ... - tailieumienphi.vn