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  1. Chương 17: THÖÏC HAØNH I. Vieát chöông trình dòch 8 led töø traùi sang phaûi vaø ngöôïc laïi 1. Moâ hình Duøng chöông trình Graphic Editor cuûa phaàn meàm Maxplus coù hoã trôï moät soá IC ñôn giaûn nhö: caùc coång, IC ñeám, ña hôïp… vaø coù theå moâ phoûng chöông trình ñaõ bieân soaïn. Nhö baøi beân döôùi, ta ñöa ra moâ hình goàm IC ñeám 4 bit vaø IC giaûi maõ 74LS138. Khi coù xung thì boä ñeám 4 bit seõ baét ñaàu ñeám töø 0000 ñeán 1111 nhöng ta chæ caàn ñeám töø 000 ñeán 111 neân chæ choïn 3 ngoõ ra töø QA, QB, QC vaø töø tín hieäu ra cuûa boä ñeám, ta cho noù laø tín hieäu vaøo cuûa IC giaûi maõ 74138 laàn löôït ñöôïc giaûi maõ töø Y0 ñeán Y7. Khi ñoù, ñeøn ñöôïc noái vôùi tín hieäu ra Y seõ laøm ñeøn saùng tuaàn töï. 2. Chöông trình Böôùc 1: Vieát caùc chöông trình rieâng a. Chöông trình chia taàn soá Vì taàn soá toaøn cuïc cuûa KIT quaù lôùn (25 MHz) neân ta khoâng theå quan saùt ñöôïc. Do ñoù, ta phaûi chia taàn soá xuoáng khoaûng 1Hz.
  2. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clk_div IS PORT ( clock_25Mhz : IN STD_LOGIC; clock_1MHz : OUT STD_LOGIC; clock_100KHz : OUT STD_LOGIC; clock_10KHz : OUT STD_LOGIC; clock_1KHz : OUT STD_LOGIC; clock_100Hz : OUT STD_LOGIC; clock_10Hz : OUT STD_LOGIC; clock_1Hz : OUT STD_LOGIC); END clk_div; ARCHITECTURE a OF clk_div IS SIGNAL count_1Mhz: STD_LOGIC_VECTOR (4 DOWNTO 0); SIGNAL count_100Khz, count_10Khz, count_1Khz: STD_LOGIC_VECTOR (2 DOWNTO 0); SIGNAL count_100hz, count_10hz, count_1hz: STD_LOGIC_VECTOR (2 DOWNTO 0);
  3. SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC; SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int: STD_LOGIC; BEGIN PROCESS BEGIN --Chia 25 WAIT UNTIL clock_25Mhz 'EVENT AND clock_25Mhz = '1'; IF count_1Mhz < 24 THEN count_1Mhz
  4. END PROCESS; --Chia 10 PROCESS BEGIN WAIT UNTIL clock_1Mhz_int 'EVENT AND clock_1Mhz_int = '1'; IF count_100Khz /= 4 THEN count_100Khz
  5. BEGIN WAIT UNTIL clock_10Khz_int 'EVENT AND clock_10Khz_int = '1'; IF count_1Khz /= 4 THEN count_1Khz
  6. count_10hz
  7. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fft IS PORT (clk : IN STD_LOGIC; B : OUT STD_LOGIC); END fft; ARCHITECTURE bb OF fft IS SIGNAL C: STD_LOGIC; BEGIN PROCESS (clk) BEGIN B
  8. USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY cf IS PORT ( clk_25MHz : IN STD_LOGIC; clk_1Hz : OUT STD_LOGIC); END cf; ARCHITECTURE bb OF cf IS COMPONENT fft PORT ( clk : IN STD_LOGIC; B : OUT STD_LOGIC); END COMPONENT; SIGNAL B, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22 : STD_LOGIC; BEGIN X1:fft PORT MAP (clk => clk_25MHz, B => B); X2:fft PORT MAP (clk => B, B => B1); X3:fft PORT MAP (clk => B1, B => B2); X4:fft PORT MAP (clk => B2, B => B3); X5:fft PORT MAP (clk => B3, B => B4); X6:fft PORT MAP (clk => B4, B => B5); X7:fft PORT MAP (clk => B5, B => B6); X8:fft PORT MAP (clk =>B6, B => B7); X9:fft PORT MAP (clk => B7, B => B8); X10:fft PORT MAP (clk => B8, B => B9); X11:fft PORT MAP (clk => B9, B => B10); X12:fft PORT MAP (clk => B10, B => B11); X13:fft PORT MAP (clk => B11, B => B12);
  9. X14:fft PORT MAP (clk => B12, B => B13); X15:fft PORT MAP (clk => B13, B => B14); X16:fft PORT MAP (clk => B14, B => B15); X17:fft PORT MAP (clk => B15, B => B16); X18:fft PORT MAP (clk => B16, B => B17); X19:fft PORT MAP (clk => B17, B => B18); X20:fft PORT MAP (clk => B18, B => B19); X21:fft PORT MAP (clk => B19, B => B20); X22:fft PORT MAP (clk => B20, B => B21); X23:fft PORT MAP (clk => B21, B => B22); X24:fft PORT MAP (clk => B22, B => clk _1Hz); END; b. Chöông trình ñeám Ta vieát chöông trình ñeám ñeán 8: töø ‘000’ ñeán 111. Do ñoù chæ caàn coù caùc tín hieäu nhö: xung (clk) vaø 1 thanh ghi COUNT (3 bit) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Counter IS PORT ( Clock : IN STD_LOGIC; Count : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); END Counter;
  10. ARCHTECTURE behavior OF Counter IS SIGNAL internal_count: STD_LOGIC_VECTOR (2 DOWNTO 0); BEGIN PROCESS (Clock) BEGIN IF (clock'EVENT AND clock='1') THEN internal_count
  11. ENTITY dahop IS PORT ( Ai : IN STD_LOGIC_VECTOR (2 DOWNTO 0); A, B, C, D, E, F, G, H : OUT STD_LOGIC); END dahop; ARCHITECTURE baby OF dahop IS SIGNAL Y: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN PROCESS (Ai) BEGIN CASE Ai (2 DOWNTO 0) IS WHEN "000" => Y Y Y Y Y Y Y Y
  12. Y