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242 CHAPTER 6 DATAPATH AND CONTROL that we can include a time delay between inputs and outputs, using the after keyword. In this case, the event computing the value of F_OUT will be triggered 4 ns after a change in any of the input values. It is also possible to specify the architecture at a level closer to the hardware by specifying logic gates instead of logic equations. This is referred to as a structural model. Here is such a specification: Structural model for the majority component In generating a structural model for the MAJORITY entity we will follow the gate design given in Figure 6-25b. We begin the model by describing a collection of logic operators, in a special construct of VHDL known as a package. The package is assumed to be stored in a working library called WORK. Following the package specification we repeat the entity declaration, and then, using the package and entity declarations we specify the internal workings of the majority component by specifying the architecture at a structural level: -- Package declaration, in library WORK package LOGIC_GATES is component AND3 port (A, B, C : in BIT; X : out BIT); end component; component OR4 port (A, B, C, D : in BIT; X : out BIT); end component; component NOT1 port (A : in BIT; X : out BIT); end component; -- Interface entity MAJORITY is port (A_IN, B_IN, C_IN F_OUT end MAJORITY; : in BIT : out BIT); -- Body -- Uses components declared in package LOGIC_GATES -- in the WORK library -- import all the components in WORK.LOGIC_GATES use WORK.LOGIC_GATES.all architecture LOGIC_SPEC of MAJORITY is -- declare signals used internally in MAJORITY signal A_BAR, B_BAR, C_BAR, I1, I2, I3, I4: BIT; begin -- connect the logic gates NOT_1 : NOT1 port map (A_IN, A_BAR); NOT_2 : NOT1 port map (B_IN, B_BAR); NOT_3 : NOT1 port map (C_IN, C_BAR); CHAPTER 6 DATAPATH AND CONTROL 243 AND_1 : AND3 port map (A_BAR, B_IN, C_IN, I1); AND_2 : AND3 port map (A_IN, B_BAR, C_IN, I2); AND_3 : AND3 port map (A_IN, B_IN, C_BAR, I3); AND_4 : AND3 port map (A_IN, B_IN, C_IN, I4); OR_1 : OR3 port map (I1, I2, I3, I4, F_OUT); end LOGIC_SPEC; The package declaration supplies three gates, a 3-input AND gate, AND3, a 4-input OR gate, OR4, and a NOT gate, NOT1. The architectures of these gates are assumed to be declared elsewhere in the package. The entity declara-tion is unchanged, as we would expect, since it specifies MAJORITY as a “black box.” The body specification begins with a use clause, which imports all of the dec-larations in the LOGIC_GATES package within the WORK library. The sig-nal declaration declares seven BIT signals that will be used internally. These signals are used to interconnect the components within the architecture. The instantiations of the three NOT gates follow, NOT_1, NOT_2, and NOT_3, all of which are NOT1 gates, and the mapping of their input and out-put signals are specified, following the port map keywords. Signals at the inputs and outputs of the logic gates are mapped according to the order in which they were declared within the package. The rest of the body specification connects the NOT gates, the AND gates, and the OR gate together as shown in Figure 6-25b. Notice that this form of architecture specification separates the design and imple-mentation of the logic gates from the design of the MAJORITY entity. It would be possible to have several different implementations of the logic gates in differ-ent packages, and to use any one of them by merely changing the uses clause. 6.4.4 9-VALUE LOGIC SYSTEM This brief treatment of VHDL only gives a small taste of the scope and power of the language. The full language contains capabilities to specify clock signals and various timing mechanisms, sequential processes, and several different kinds of signals. There is an IEEE standard 9-value logic system, known as STD_ULOGIC, IEEE 1164-1993. It has the following logic values: type STD_ULOGIC is ( ‘U’, -- Uninitialized 244 CHAPTER 6 DATAPATH AND CONTROL ‘X’, -- Forcing unknown ‘0’, -- Forcing 0 ‘1’, -- Forcing 1 ‘Z’, -- High impedance ‘W’, -- Weak unknown ‘L’, -- Weak 0 ‘H’, -- Weak 1 ‘-’, -- Don’t care ); Without getting into too much detail, these values allow the user to detect logic flaws within a design, and to follow the propagation of uninitialized or weak sig-nals through the design. SUMMARY A microarchitecture consists of a datapath and a control section. The datapath contains data registers, an ALU, and the connections among them. The control section contains registers for microinstructions (for a microprogramming approach) and for condition codes, and a controller. The controller can be micro-programmed or hardwired. A microprogrammed controller interprets microin-structions by executing a microprogram that is stored in a control store. A hardwired controller is organized as a collection of flip-flops that maintain state information, and combinational logic that implements transitions among the states. The hardwired approach is fast, and consumes a small amount of hardware in comparison with the microprogrammed approach. The microprogrammed approach is flexible, and simplifies the process of modifying the instruction set. The control store consumes a significant amount of hardware, which can be reduced to a degree through the use of nanoprogramming. Nanoprogramming adds delay to the microinstruction execution time. The choice of microprogrammed or hard-wired control thus involves trade-offs: the microprogrammed approach is large and slow, but is flexible and lends itself to simple implementations, whereas the hardwired approach is small and fast, but is difficult to modify, and typically results in more complicated implementations. CHAPTER 6 DATAPATH AND CONTROL 245 FURTHER READING (Wilkes, 1958) is a classic reference on microprogramming. (Mudge, 1978) cov-ers microprogramming on the DEC PDP 11/60. (Tanenbaum, 1990) and (Mano, 1991) provide instructional examples of microprogrammed architec-tures. (Hill and Peterson, 1987) gives a tutorial treatment of the AHPL hardware description language, and hardwired control in general. (Lipsett et. al., 1989) and (Navabi, 1993) describe the commercial VHDL hardware description lan-guage and provide examples of its use. (Gajski, 1988) covers various aspects of silicon compilation. Gajski, D., Silicon Compilation, Addison Wesley, (1988). Hill, F. J. and G. R. Peterson, Digital Systems: Hardware Organization and Design, 3/e, John Wiley & Sons, (1987). Lipsett, R., C. Schaefer, and C. Ussery, VHDL: Hardware Description and Design, Kluwer Academic Publishers, (1989). Mano, M., Digital Design, 2/e, Prentice Hall, (1991). Mudge, J. Craig, Design Decisions for the PDP11/60 Mid-Range Minicomputer, in Computer Engineering, A DEC View of Hardware Systems Design, Digital Press, Bedford MA, (1978). Navabi, Z., VHDL: Analysis and Modeling of Digital Systems, McGraw Hill, (1993). Tanenbaum, A., Structured Computer Organization, 3/e, Prentice Hall, Engle-wood Cliffs, New Jersey, (1990). Wilkes, M. V., W. Redwick, and D. Wheeler, “The Design of a Control Unit of an Electronic Digital Computer,” Proc. IRE, vol. 105, p. 21, (1958). PROBLEMS 6.1 Design a 1-bit arithmetic logic unit (ALU) using the circuit shown in Fig-ure 6-26 that performs bitwise addition, AND, OR, and NOT on the 1-bit inputs A and B. A 1-bit output Z is produced for each operation, and a carry is also produced for the case of addition. The carry is zero for AND, OR, and 246 CHAPTER 6 DATAPATH AND CONTROL Function F0 Select F1 2-to-4 Decoder Output Z 00 01 10 11 Carry X Y Out Data A Inputs B Carry In Carry In Full Adder Carry Out Sum Fo F1 Function 0 0 ADD(A,B) 0 1 AND(A,B) 1 0 OR(A,B) 1 1 NOT(A) Figure 6-26 A one-bit ALU. NOT. Design the 1-bit ALU using the components shown in the diagram. Just draw the connections among the components. Do not add any logic gates, MUXes, or anything else. Note: The Full Adder takes two one-bit inputs (X and Y) and a Carry In, and produces a Sum and a Carry Out. 6.2 Design an ALU that takes two 8-bit operands X and Y and produces an 8-bit output Z. There is also a two-bit control input C in which 00 selects log-ical AND, 01 selects OR, 10 selects NOR, and 11 selects XOR. In designing your ALU, follow this procedure: (1) draw a block diagram of eight 1-bit ALUs that each accept a single bit from X and Y and both control bits, and produce the corresponding single-bit output for Z; (2) create a truth table that describes a 1-bit ALU; (3) design one of the 1-bit ALUs using an 8-to-1 MUX. 6.3 Design a control unit for a simple hand-held video game in which a char-acter on the display catches objects. Treat this as an FSM problem, in which you only show the state transition diagram. Do not show a circuit. The input to the control unit is a two-bit vector in which 00 means “Move Left,” 01 means “Move Right,” 10 means “Do Not Move,” and 11 means “Halt.” The output Z is 11 if the machine is halted, and is 00, 01, or 10 otherwise, corre-sponding to the input patterns. Once the machine is halted, it must remain in the halted state indefinitely. ... - tailieumienphi.vn
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