Tài liệu miễn phí Điện - Điện tử

Download Tài liệu học tập miễn phí Điện - Điện tử

Lecture Digital Logic & Design: Lesson 41

Lecture Digital Logic & Design: Lesson 41 provide students with knowledge about memory; DRAM access: DRAM read cycle (fig 1a), DRAM write cycle (fig 1b), FAST page access mode (fig 2); DRAM refresh: burst refresh 1024 row refreshed in 8 ms, distributed refresh single row refreshed in 7.8 microsec, RAS only refresh;...

4/7/2023 11:02:58 PM +00:00

Lecture Digital Logic & Design: Lesson 40

Lecture Digital Logic & Design: Lesson 40 provide students with knowledge about memory array decoded by row and columns decoders; input/output data circuit; timing diagram of a read cycle; timing diagram of a write cycle; block diagram of a synchronous burst RAM; burst logic circuit;...

4/7/2023 11:02:47 PM +00:00

Lecture Digital Logic & Design: Lesson 39

Lecture Digital Logic & Design: Lesson 39 provide students with knowledge about 64-cell memory array; memory organized as 4 x 16 and 1 x 64 arrays; block diagram of a read-write memory; memory read operation; memory write operation; circuit diagram of a static memory cell based on a flip-flop;...

4/7/2023 11:02:40 PM +00:00

Lecture Digital Logic & Design: Lesson 38

Lecture Digital Logic & Design: Lesson 38 provide students with knowledge about equation definition for the traffic light controller; the circuit diagram of the traffic light controller; pin declarations for the turning on/off traffic lamps; switching of traffic lamps at different states;...

4/7/2023 11:02:31 PM +00:00

Lecture Digital Logic & Design: Lesson 37

Lecture Digital Logic & Design: Lesson 37 provide students with knowledge about SR1 latch which stores the status of the REQ1, FLOOR1 and OPEN buttons; simplified state table for elevator control for REQ1, FLOOR1 and OPEN inputs; modified block diagram of the elevator state machine;...

4/7/2023 11:02:25 PM +00:00

Lecture Digital Logic & Design: Lesson 36

Lecture Digital Logic & Design: Lesson 36 provide students with knowledge about boolean expression for D2 inputs; 3-bit up/down counter; input/output pin definition of 3-bit up/down counter; equation definition of 3-bit up/down counter; test vector definition of 3-bit up/down counter;...

4/7/2023 11:02:18 PM +00:00

Lecture Digital Logic & Design: Lesson 35

Lecture Digital Logic & Design: Lesson 35 provide students with knowledge about 11-bit serial data format; series-to-parallel converter; keyboard encoder circuit; OLMC of the GAL22V10 device; software mode specification; assignment operators for registered mode; ABEL input file of an 8-bit register with inverted outputs;...

4/7/2023 11:02:12 PM +00:00

Lecture Digital Logic & Design: Lesson 34

Lecture Digital Logic & Design: Lesson 34 provide students with knowledge about serial in/serial right/serial out operation; serial in/serial left/serial out operation; timing diagram of a serial in/shift right/serial out register; timing diagram of a Bi-directional, 4-bit shift register;...

4/7/2023 11:02:06 PM +00:00

Lecture Digital Logic & Design: Lesson 33

Lecture Digital Logic & Design: Lesson 33 provide students with knowledge about three possible state assignments for states; next state flip-flop input table for first state assignment; next state flip-flop input table for second state assignment; next state flip-flop input table for third state assignment;...

4/7/2023 11:01:59 PM +00:00

Lecture Digital Logic & Design: Lesson 32

Lecture Digital Logic & Design: Lesson 32 provide students with knowledge about sequential logic; design of D sync. counters: flip-flop transition table (tab 1), flip-flop input table (tab 2), Karnaugh maps (tab 3), logical expressions for flip-flop inputs, sequential circuit Implementation (fig 1a), iiming diagram (fig 1b);...

4/7/2023 11:01:53 PM +00:00

Lecture Digital Logic & Design: Lesson 31

Lecture Digital Logic & Design: Lesson 31 provide students with knowledge about next-state table for a 3-bit up-counter; J-K flip-flop transition table; J-K flip-flop input table; Karnaugh map for J2 and K2 inputs; implementation of the sequential circuit; S-R flip-flop transition table;...

4/7/2023 11:01:47 PM +00:00

Lecture Digital Logic & Design: Lesson 30

Lecture Digital Logic & Design: Lesson 30 provide students with knowledge about counter applications; digital counter; frequency counter (fig 3a, 3b); timing diagram of the divide by 60 minutes/seconds counter; hours counter timing diagram; frequency counter circuit;...

4/7/2023 11:01:40 PM +00:00

Lecture Digital Logic & Design: Lesson 29

Lecture Digital Logic & Design: Lesson 29 provide students with knowledge about sequential logic; up-down synchronous counter; timing diagram of an up-down synchronous counter; 74HC190 4-bit synchronous up/down counter; decoder circuit decoding counter outputs 4, 8 and 12;...

4/7/2023 11:01:34 PM +00:00

Lecture Digital Logic & Design: Lesson 28

Lecture Digital Logic & Design: Lesson 28 provide students with knowledge about synchronous decade counter; timing diagram of a synchronous decade counter; 74HC163 4-bit synchronous counter; timing diagram of the 74HC163 synchronous counter; cascaded decade counters;...

4/7/2023 11:01:27 PM +00:00

Lecture Digital Logic & Design: Lesson 27

Lecture Digital Logic & Design: Lesson 27 provide students with knowledge about sequential logic; asynchronous counters: down counters (fig 1), down counter with truncated sequence (fig 2); synchronous counters: synchronous counter (fig 3), synchronous decade counter (tab 1 fig 6);...

4/7/2023 11:01:21 PM +00:00

Lecture Digital Logic & Design: Lesson 26

Lecture Digital Logic & Design: Lesson 26 provide students with knowledge about J-K flip-flop circuit with potential timing problem; timing diagram of J-K flip-flop circuit with potential timing problem; Flip-flop circuit with potential timing problem due to clock; timing diagram of J-K flip-flop circuit with clock skew;...

4/7/2023 11:01:14 PM +00:00

Lecture Digital Logic & Design: Lesson 25

Lecture Digital Logic & Design: Lesson 25 provide students with knowledge about J-K flip-flop with asynchronous preset and clear inputs; logic symbol of a J-K flip-flop with asynchronous inputs; truth table of J-K flip-flop with asynchronous inputs; timing diagram of a J-K flip-flop with preset and clear inputs;...

4/7/2023 11:01:08 PM +00:00

Digital Logic & Design - Lec_24

Lecture Digital Logic & Design: Lesson 24 provide students with knowledge about sequential logic; D flip-flop applications: data storage (fig 1, 2), synchronizing asynchronous inputs (fig 3,4,5,6), parallel data transfer (fig 7); J-K flip-flop and J-K flip-flop applications;...

4/7/2023 11:01:01 PM +00:00

Lecture Digital Logic & Design: Lesson 23

Lecture Digital Logic & Design: Lesson 23 provide students with knowledge about sequential logic; latch applications; the output of a switch connected to logic high; truth-table of positive and negative edge triggered D flip-flops; timing diagram of a Negative Edge triggered S-R flip-flop;...

4/7/2023 11:00:55 PM +00:00

Lecture Digital Logic & Design: Lesson 22

Lecture Digital Logic & Design: Lesson 22 provide students with knowledge about sequential logic; ABEL input file (tab 1 fig 1); implementation of MUX (fig 2); latches and flip-flops; latch applications; logic symbols (fig 5); timing diagrams (fig 6);...

4/7/2023 11:00:48 PM +00:00

Lecture Digital Logic & Design: Lesson 21

Lecture Digital Logic & Design: Lesson 21 provide students with knowledge about programmable logic devices; GAL16V8: emulate PALs three modes, OLMC; GAL16V8: simple mode (3 options), complex mode (2 options), registered mode; ABEL: acronym advanced boolean expression language;...

4/7/2023 11:00:41 PM +00:00

Lecture Digital Logic & Design: Lesson 20

Lecture Digital Logic & Design: Lesson 20 provide students with knowledge about programmable logic devices; PLA: implementing constant 0s and 1s (fig 1), implementing odd-prime number (fig 2); GALs: generic array logic structure (fig 3, 4), output logic macro cells OLMCs (fig 5), GAL ID (fig 6), programming of GAL;...

4/7/2023 11:00:35 PM +00:00

Lecture Digital Logic & Design: Lesson 19

Lecture Digital Logic & Design: Lesson 19 provide students with knowledge about programmable logic devices; programmable OR/AND gate arrays (fig 3); programmed OR/AND gate arrays (fig 4); PLD types: PROM (fig 5), PLA (fig 6), PAL (fig 7), GAL (fig 8); PAL programmed for SOP (fig 9);...

4/7/2023 11:00:29 PM +00:00

Lecture Digital Logic & Design: Lesson 18

Lecture Digital Logic & Design: Lesson 18 provide students with knowledge about combinational functional devices; MUX applications: 2-digit decimal display circuit (fig 5), common cathode/anode displays (fig 6), 2-digit mux based display circuit (fig 7);...

4/7/2023 11:00:21 PM +00:00

Lecture Digital Logic & Design: Lesson 17

Lecture Digital Logic & Design: Lesson 17 provide students with knowledge about combinational functional devices; cascading ALUs without G.Carry (fig 1); cascading ALUs with G.Carry (fig 2); 16-bit ALU circuit (fig 3); cascading of comparators (tab 1 fig 5); iterative comparator (fig 6); MSI comparator (fig 7);...

4/7/2023 11:00:13 PM +00:00

Lecture Digital Logic & Design: Lesson 16

Lecture Digital Logic & Design: Lesson 16 provide students with knowledge about carry propagation delay between 4-bit ALU units; carry propagation delay eliminated by using group carry; parallel comparators; comparison of numbers by cascaded 4-bit comparator; implementation of 4-bit comparator by cascading two 2-bit comparators;...

4/7/2023 11:00:06 PM +00:00

Lecture Digital Logic & Design: Lesson 15

Lecture Digital Logic & Design: Lesson 15 provide students with knowledge about combinational functional devices; BCD addition and error conditions; single digit BCD adder circuit (fig 1); BCD error detection ckt. (tab 1,fig 2,3); connection of error detection ckt. (fig4);...

4/7/2023 10:59:55 PM +00:00

Lecture Digital Logic & Design: Lesson 14

Lecture Digital Logic & Design: Lesson 14 provide students with knowledge about combinational functional devices; odd-parity function; SOP expression simplification; simplifying expression; odd-parity generator circuit; XOR & XNOR gates; parity generator circuit;...

4/7/2023 10:59:49 PM +00:00

Lecture Digital Logic & Design: Lesson 13

Lecture Digital Logic & Design: Lesson 13 provide students with knowledge about odd prime number; combinational logic: implementation of SOP using AND-OR, implementation of POS using OR-AND; design and implementation of digital circuits; adjacent 1s detector circuit;...

4/7/2023 10:59:42 PM +00:00

Lecture Digital Logic & Design: Lesson 12

Lecture Digital Logic & Design: Lesson 12 provide students with knowledge about comparator circuit; function table for A>B; function table for A=B; function table for A

4/7/2023 10:59:35 PM +00:00