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9.6 Summary
In this chapter, we discussed the following aspects of Verilog:
• Procedural continuous assignments can be used to override the
assignments on registers and nets. assign and deassign can override
assignments on registers. force and release can override assignments on
registers and nets. assign and deassign are used in the actual design.
force and release are used for debugging.
• Parameters defined in a module can be overridden with the defparam
statement or by passing a new value during module instantiation.
During module instantiation, parameter values can be assigned by
ordered list or by name. It is recommended to use parameter
assignment by name.
• Compilation of parts of the design can be made conditional by using
the 'ifdef, 'ifndef, 'elsif, 'else, and 'endif directives. Compilation flags
are defined at compile time by using the `define statement.
• Execution is made conditional in Verilog simulators by means of the
$test$plusargs system task. The execution flags are defined at run time
by +.
• Up to 30 files can be opened for writing in Verilog. Each file is
assigned a bit in the multichannel descriptor. The multichannel
descriptor concept can be used to write to multiple files. The IEEE
Standard Verilog Hardware Description Language document describes
more advanced ways of doing file I/O.
• Hierarchy can be displayed with the %m option in any display
statement.
• Strobing is a way to display values at a certain time or event after all
other statements in that time unit have executed.
• Random numbers can be generated with the system task $random. They
are used for random test vector generation. $random task can generate
both positive and negative numbers.
• Memory can be initialized from a data file. The data file contains
addresses and data. Addresses can also be specified in memory
initialization tasks.
- • Value Change Dump is a popular format used by many designers for
debugging with postprocessing tools. Verilog allows all or selected
module variables to be dumped to the VCD file. Various system tasks
are available for this purpose.
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9.7 Exercises
1: Using assign and deassign statements, design a positive edge-
triggered D-flipflop with asynchronous clear (q=0) and preset (q=1).
2: Using primitive gates, design a 1-bit full adder FA. Instantiate the full
adder inside a stimulus module. Force the sum output to a & b & c_in
for the time between 15 and 35 units.
3: A 1-bit full adder FA is defined with gates and with delay parameters
as shown below.
// Define a 1-bit full adder
module fulladd(sum, c_out, a, b, c_in);
parameter d_sum = 0, d_cout = 0;
// I/O port declarations
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, c2;
// Instantiate logic gate primitives
xor (s1, a, b);
and (c1, a, b);
xor #(d_sum) (sum, s1, c_in); //delay on output sum is d_sum
and (c2, s1, c_in);
- or #(d_cout) (c_out, c2, c1); //delay on output c_out is d_cout
endmodule
Define a 4-bit full adder fulladd4 as shown in Example 5-8 on page
77, but pass the following parameter values to the instances, using the
two methods discussed in the book:
Instance Delay Values
fa0 d_sum=1, d_cout=1
fa1 d_sum=2, d_cout=2
fa2 d_sum=3, d_cout=3
fa3 d_sum=4, d_cout=4
a. Build the fulladd4 module with defparam statements to change
instance parameter values. Simulate the 4-bit full adder using
the stimulus shown in Example 5-9 on page 77. Explain the
effect of the full adder delays on the times when outputs of the
adder appear. (Use delays of 20 instead of 5 used in this
stimulus.)
b. Build the fulladd4 with delay values passed to instances fa0,
fa1, fa2, and fa3 during instantiation. Resimulate the 4-bit
adder, using the stimulus above. Check if the results are
identical.
4: Create a design that uses the full adder example above. Use a
conditional compilation (`ifdef). Compile the fulladd4 with defparam
statements if the text macro DPARAM is defined by the `define
statement; otherwise, compile the fulladd4 with module instance
parameter values.
5: Identify the files to which the following display statements will write:
- //File output with multi-channel descriptor
module test;
integer handle1,handle2,handle3; //file handles
//open files
initial
begin
handle1 = $fopen("f1.out");
handle2 = $fopen("f2.out");
handle3 = $fopen("f3.out");
end
//Display statements to files
initial
begin
//File output with multi-channel descriptor
#5;
$fdisplay(4, "Display Statement # 1");
$fdisplay(15, "Display Statement # 2");
$fdisplay(6, "Display Statement # 3");
$fdisplay(10, "Display Statement # 4");
$fdisplay(0, "Display Statement # 5");
end
endmodule
6: What will be the output of the $display statement shown below?
module top;
A a1();
endmodule
module A;
B b1();
endmodule
- module B;
initial
$display("I am inside instance %m");
endmodule
7: Consider the 4-bit full adder in Example 6-4 on page 108. Write a
stimulus file to do random testing of the full adder. Use a random
number generator to generate a 32-bit random number. Pick bits 3:0
and apply them to input a; pick bits 7:4 and apply them to input b.
Use bit 8 and apply it to c_in. Apply 20 random test vectors and
observe the output.
8: Use the 8-byte memory initialization example in Example 9-14 on
page 205. Modify the file to read data in hexadecimal. Write a new
data file with the following addresses and data values. Unspecified
locations are not initialized.
Location Address Data
1 33
2 66
4 z0
5 0z
6 01
9: Write an initial block that controls the VCD file. The initial block
must do the following:
• Set myfile.dmp as the output VCD file.
• Dump all variables two levels deep in module instance
top.a1.b1.c1.
• Stop dumping to VCD at time 200.
• Start dumping to VCD at time 400.
• Stop dumping to VCD at time 500.
- • Create a checkpoint. Dump the current value of all VCD
variables to the dumpfile.
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