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MICROCOMPUTER INSTRUMENTATION AND CONTROL 4 Microprocessor Architecture Understanding how the microprocessor operates is aided by Figure 4.6, which is a block diagram of a typical commercial microprocessor. This block diagram is divided into two main portions—a register section and a control section. The actual operations performed by the microprocessor are Figure 4.6 Typical Microprocessor Internal Architecture FPO UNDERSTANDING AUTOMOTIVE ELECTRONICS 109 4 MICROCOMPUTER INSTRUMENTATION AND CONTROL accomplished in the register section. The specific operations performed during the execution of a given step in the program are controlled by electrical signals from the instruction decoder. During each program step, an instruction in the form of an 8-bit (or possibly 16-bit) number is transferred from memory to the instruction register. This instruction is decoded using logic circuits similar to those presented in Chapter 3. The result of this decoding process is a set of electrical control signals that are sent to the specific components of the register section that are involved in the instruction being executed. The data upon which the operation is performed is similarly transferred from memory to the data bus buffer. From this buffer the data is then transferred to the desired component in the register section for execution of the operation. Note that an arithmetic and logic unit (ALU) is included in the register section of the typical microprocessor is shown in Figure 4.6. This device is a complex circuit capable of performing the arithmetic and logical operations, as explained in Chapter 3. Also included in the register section is the accumulator, which is the register used most frequently to receive the results of arithmetic or logical operation. In addition, the example microprocessor register section has an index register, stack pointer register, and program counter register. The program counter register holds the contents of the program counter and is connected through the internal address bus to the address buffer register. The address bus for the example microprocessor has 16 lines, and thereby can directly address 65,536 (i.e., 64K) of memory. READING INSTRUCTIONS To understand how the computer performs a branch, one must first understand how the computer reads program instructions from memory. Recall that program instructions are stored sequentially (step by step) in memory as binary numbers, starting at a certain binary address and ending at some higher address. The computer uses a register called the program counter (Figure 4.4) to keep track of where it is in the program. The first step in starting up a computer is initial-ization. 110 Initialization To start the computer, a small startup (boot) program that is permanently stored in the computer is run. This program sets all of the CPU registers with the correct values and clears all information in the computer memory to zeros before the operations program is loaded. This is called initializing the system. Then, the operations program is loaded into memory, at which point the address of the first program instruction is loaded into the program counter. The first instruction is read from the memory location whose address is contained in UNDERSTANDING AUTOMOTIVE ELECTRONICS MICROCOMPUTER INSTRUMENTATION AND CONTROL 4 the program counter register; that is, the 16 bits in the program counter are used as the address for a memory read operation. Each instruction is read from memory in sequence and set on the data bus into the instruction register, where it is decoded. The instruction register is another temporary storage register inside the CPU (or microprocessor). It is connected to the data bus when the information on the bus is an instruction. The actual instructions in the program are in the form of numeric codes called operation codes (op codes). Instructions often are contained in more than one byte. In such cases, the first byte contains the op code, and suc-ceeding bytes contain the address. Each successive read of a memory location causes the program counter to be incremented to the address of the next byte. Operation Codes Numeric codes called operation codes (or op codes for short) contain the instructions that represent the actual operation to be performed by the CPU. The block diagram of Figure 4.7, which illustrates part of the CPU hardware organization, should help clarify the flow of instructions through the CPU. The instruction register has a part that contains the numeric op codes. A decoder determines from the op codes the operation to be executed, and a data register controls the flow of data inside the CPU as a result of the op code instructions. One important function of the op-code decoder is to determine how many bytes must be read to execute each instruction. Many instructions require two or three bytes. Figure 4.8 shows the arrangement of the bytes in an instruction. The first byte contains the op code. The second byte contains address information, usually the low or least significant byte of the address. Program Counter The program counter is used by the CPU to address memory locations that contain instructions. Every time an op code is read (this is often called fetched) from memory, the program counter is incremented (advanced by one) so that it points to (i.e., contains the address of) the next byte following the op code. If the operation code requires another byte, the program counter supplies the address, the second byte is fetched from memory, and the program counter is incremented. Each time the CPU performs a fetch operation, the program counter is incremented; thus, the program counter always points to the next byte in the program. Therefore, after all bytes required for one complete instruction have been read, the program counter contains the address for the beginning of the next instruction to be executed. Branch Instruction All of the branch instructions require two bytes. The first byte holds the operation code, and the second byte holds the location to which the processor is to branch. UNDERSTANDING AUTOMOTIVE ELECTRONICS 111 4 MICROCOMPUTER INSTRUMENTATION AND CONTROL Figure 4.7 CPU Organization FPO A positive branch offset address results in a branch to a higher mem-ory location, while a negative branch offset address results in a branch to a lower mem-ory location. 112 Now, if the address information associated with a branch instruction is only 8 bits long and totally contained in the second byte, it cannot be the actual branch address. In this case, the code contained in the second byte is actually a two’s complement number that the CPU adds to the lower byte of the program counter to determine the actual new address. This number in the second byte of the branch instruction is called an address offset or just offset. Recall that in two’s complement notation, the 8-bit number can be either positive or negative; therefore, the branch address offset can be positive or negative. A positive branch offset causes a branch forward to a higher memory location. A negative branch offset causes a branch to a lower memory location. Since 8 bits are used UNDERSTANDING AUTOMOTIVE ELECTRONICS MICROCOMPUTER INSTRUMENTATION AND CONTROL 4 Figure 4.8 Instruction Byte Arrangement FPO 8-bit branch operations are limited to an offset range of +127 or –128 memory locations. Thus, program branches to locations farther away must use jump instruc-tions. These 3-byte instructions contain the entire memory address. in the present example, the largest forward branch is 127 memory locations and the largest backward branch is 128 memory locations. Offset Example Suppose the program counter is at address 5,122 and the instruction at this location is a branch instruction. The instruction to which the branch is to be made is located at memory address 5,218. Since the second byte of the branch instruction is only 8 bits wide, the actual address 5,218 cannot be contained therein. Therefore, the difference or offset (96) between the current program counter value (5,122) and the desired new address (5,218) is contained in the second byte of the branch instruction. The offset value (96) is added to the address in the program counter (5,122) to obtain the new address (5,218), which is then placed on the address bus. The binary computation of the final address from the program counter value and second byte of the branch instruction is shown in Figure 4.9 Jump Instruction Branch instructions have a range of +127 or –128 (in the present 8-bit example). If the branch needs to go beyond this range, a jump instruction must be used. The jump instruction is a 3-byte instruction. The first byte is the jump op code, and the next two bytes are the actual jump address. The CPU loads the jump address directly into the program counter, and the program counter effectively gets restarted at the new jump location. The CPU continues to fetch and execute instructions in exactly the same way it did before the jump was made. The jump instruction causes the CPU to jump out of one section of the program into another. The CPU cannot automatically return to the first section because no record was kept of the previous location. However, another instruction, the jump-to-subroutine, does leave a record of the previous instruction address. UNDERSTANDING AUTOMOTIVE ELECTRONICS 113 ... - tailieumienphi.vn
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