the PCI Bus demystified phần 7

C H A P T E R 8 PCI Bridging The notion of bridging plays a significant role in PCI architecture primarily due to electrical limitations that impose a severe limit on the number of devices residing on a single PCI bus segment. In some cases it is also desirable to functionally isolate portions of the system so they can operate in parallel. Bridge Types In this chapter we’re primarily concerned with the PCI-to-PCI (P2P) bridge, that is, a bridge that connects two PCI bus segments. The P2P bridge is defined in PCI-to-PCI Bridge Architecture Specifi-cation, Rev. 1.1, December 1998. But before delving into the details of the P2P bridge, we should note briefly that there are two other types of bridges that serve specific roles as illustrated in Figure 8-1. Host-to-PCI Bridge None of today’s popular processor architectures has a PCI bus coming directly off the chip. Rather, each processor defines its own local bus optimized around the specific architecture. External cache and main memory often reside on the local processor bus. Some local busses also support multiple processors. 125 PCI Bus Demystified CPU Host Cache Bus Memory Host-PCI PCI Bridge Device PCI Bus 0 PCI Option Card PCI-ISA Bridge PCI-PCI Bridge 1 PCI Bus 2 Legacy Device ISA Bus PCI-PCI PCI PCI PCI Bridge 2 Device Device Bus 1 Figure 8-1: PCI bridge hierarchy. The Host-to-PCI bridge provides the translation from the local processor bus to the PCI. In conventional PC environments, the Host-to-PCI bridge, often referred to as the “North Bridge,” is one element of the chipset and is usually contained in the same chip that manages main memory and the Level 2 cache. To the extent feasible, the architecture of the Host-to-PCI bridge mimics the P2P bridge specification. PCI-to-Legacy Bus Bridge Someday, the ISA bus will disappear from PC architecture. Some-day income tax forms will be understandable. But for the time being, “legacy” busses such as ISA and EISA are supported through the mechanism of a PCI-to-Legacy Bridge. Like the Host-to-PCI bridge, this is usually an element of the chipset that also incorporates such traditional features as IDE, interrupt and DMA controllers. Legacy bridges often implement subtractive decoding because the cards on the legacy bus aren’t plug-and-play and thus can’t be configured. The PCI-to-ISA bridge is usually referred to as the “South Bridge.” 126 PCI Bridging PCI-to-PCI Bridge A PCI-to-PCI bridge provides a connection between a primary interface and a secondary interface (see Figure 8-2). The primary inter-face is the one electrically “closer” to the host CPU. These are also referred to as the upstream bus and the downstream bus. Transactions are said to flow downstream when the initiator is on the upstream bus and the target is on the downstream bus. Conversely, transactions flow upstream when the initiator is on the downstream side and the target is on the upstream side. There is a corresponding symmetry to the structure of the bridge. When transactions flow downstream, the primary interface acts as a target and the secondary interface is the master. When transactions flow upstream, the converse is true. The secondary interface acts as the target and the primary interface is the master. Data Path Primary Interface Optional data buffers Optional data buffers Configuration Registers Data Path Secondary Interface Primary Target Interface Control Secondary Master Interface Control Primary Master Interface Secondary Target Interface Figure 8-2: PCI bridge structure. 127 PCI Bus Demystified A bridge may, and usually does, include FIFO buffering for posting write transactions and prefetching read data. One asymmetrical characteristic is that the bridge can only be configured and controlled from the primary interface. Configuration Address Types There are two configuration address formats called respectively Type 0 and Type 1. These are distinguished by the LSB of the address where Type 0 is 0 and Type 1 is 1. The difference is that Type 1 includes a device and bus number and Type 0 doesn’t (see Figure 8-3). Type 1 represents a configuration transaction directed at a target on another (downstream) bus segment whereas a Type 0 transaction is directed at a target on the bus where the transaction originated. Type 0 transactions are not forwarded across a bridge. As the Type 1 transaction passes from bridge to bridge, it eventually reaches the one whose downstream bus segment matches the bus number in the transaction. That bridge converts the Type 1 address to a Type 0 and forwards it to the downstream bus where it is executed. Type 0 31 Reserved 11 10 8 7 Function Number 2 1 0 Register Number Type 1 31 Reserved 24 23 16 15 11 10 8 7 Bus Device Function Number Number Number 2 1 0 Register Number Figure 8-3: Configuration address types. 128 PCI Bridging Configuration Header—Type 1 Figure 8-4 shows the Type 1 Configuration Header defined for the P2P bridge. The first six DWORDs of the Type 1 header are the same as the Type 0. The redefined fields are primarily concerned with identifying bus segments and establishing address windows. 31 Device ID Status 16 15 0 Vendor ID 00h Command 04h BIST* Class Code Header Type Primary Latency Revision ID 08h Cache Line Size *Optional Base Address Registers* SecondarySubordinate Secondary Primary Latency Bus # Bus # Bus # Secondary Status IO Limit* IO Base* Memory Limit Memory Base Prefetchable Prefetchable Memory Limit* Memory Base* 10h 14h 18h 1Ch 20h 24h Prefetchable Base Upper 32 bits* 28h Prefetchable Limit Upper 32 bits* 2ch IO Limit Upper 16 bits* IO Base Upper 16 bits* 30h Reserved 34h Expansion ROM Base Address* 38h Bridge Control Interrupt Interrupt 3Ch Figure 8-4: Configuration space header, Type 1. The only transactions that a bridge is required to pass through are to 32-bit non-prefetchable memory space using the Memory Base and Limit registers. This space is generally used for memory mapped I/O. Optionally the bridge may support transactions to I/O space, either 64 K or 4 Gbytes using the I/O Base and Limit registers. It may also support prefetchable transactions to 32- or 64-bit address space using the Prefetchable Base and Limit registers. 129 ... - tailieumienphi.vn