the PCI Bus demystified phần 6

PCI Bus Demystified master can retain ownership of the bus. Typically, the lower three bits are hardwired to 0 and only the upper 5 bits are writable. This yields a maximum of 255 clock cycles with a granularity of eight clock cycles. The Latency Timer may be read-only if the master never bursts more than two data phases. Cache-Line Size Configuration software writes the system cache line size in DWORD increments to this register. It is required for any master that implements the Memory Write and Invalidate command and for any target that implements cache-line wrap addressing. Masters that implement the advanced read commands should take advantage of this register to optimize their use of the read commands. Cardbus CIS Pointer Optional. Implemented by devices that share silicon between cardbus and PCI devices. It points to the Card Information Structure for the Cardbus implementation. Details of the CIS can be found in revision 3.0 of the PC Card specification. Capabilities Pointer If Status Register bit 4 = 1, this read-only byte is a pointer to the first entry of the Capabilities List. It is a byte offset into the device-specific configuration space. Max_Lat (Maximum Latency) The specification says that this optional register specifies “how often the device needs to gain access to the PCI bus”. A better inter-pretation might be how quickly the master needs access to the bus. Values of Max_Lat are in increments of 250 ns which happens to be about eight clocks at 33 MHz. 102 Plug and Play Configuration The intention is that configuration software can use this value to assign the master to an arbitration priority level. Devices with lower values, implying a need for low latency, would be assigned to the higher priority levels. Min_Gnt (Minimum Grant) This register indicates how long the master would like to retain bus ownership when it initiates a transaction. Values of Min_Gnt are in increments of 250 ns or eight clocks at 33 MHz. Configuration software uses this value to set the device’s Latency Timer. Base Address Registers (BAR) The Base Address Registers provide the mechanism that allows configuration software to determine the memory and I/O resources that a device requires. Once the system topology is determined, configuration software maps all devices into a set of reasonable, non-conflicting address ranges and writes the corresponding starting addresses into the Base Address Registers. The Type 0 configuration header supports up to six Base Address Registers, allowing a device to have up to six independent address ranges. There are two formats for the Base Register as shown in Figure 6-7. Read-only bit 0 determines whether the Base Address Register represents memory or I/O space. For memory space, read-only bits 1 and 2 indicate how the memory space must be mapped and the size of the Base Address Register. Memory can be mapped into either 32-bit or 64-bit address space implying respectively a 32-bit register or a 64-bit register. A 64-bit register occupies two adjacent BAR locations in the Configuration Header. Prior to revision 2.2 the combination 01 103 PCI Bus Demystified in bits 2 and 1 identified memory space that must be located below the one megabyte real mode boundary. Although this is no longer supported, “System software should recognize this encoding and handle appropriately.” Bit 3 identifies prefetchable memory. 31 4 3 2 1 0 Base Address 0 Prefetchable Type 00 - locate anywhere in 32-bit space 01 - reserved 10 - locate anywhere in 64-bit space 11 - reserved Memory space indicator 31 2 1 0 Base Address 1 Reserved I/O space indicator Figure 6-7: Base Address Register. For I/O space, bit 1 is hardwired to 0 and the remaining bits are used to map the device. An I/O Base Address Register is always 32 bits. Determining Block Size How does configuration software determine the size of the memory or I/O space represented by each BAR? A Base Address Register only implements as many bits as are necessary to decode the block size that it represents. Thus, for example, a BAR that represents 1 Megabyte of memory space would only need to implement the upper 12 bits of the 104 Plug and Play Configuration 32 bit address. The lower 20 bits decode an address within the 1 Megabyte range. When you read a BAR, the undecoded bits read back as 0. So the procedure for determining block size is to: Step 1 MB Example 1. Write all 1’s to the register 2. Read it back 3. Mask off the lower four read-only bits 4. Take the 1’s complement 5. Add 1. This is the block size. 0xFFFFFFFF 0xFFF00008 0xFFF00000 0x000FFFFF 0x00100000 The same procedure applies to I/O space and 64-bit memory space. This strategy has two interesting consequences. Block sizes are always powers of 2 and the base address is always “naturally aligned.” This means, for example, that a 2 MB address space can’t have a starting address of 3 MB. Note that the minimum block size inferred by the Memory BAR format is 16 bytes. Likewise the minimum I/O block size is four bytes. In the interest of minimizing the number of bits in a BAR, devices are allowed to consume more space than they actually use. The specification suggests that decoding down to 4 KB of memory space is appropriate for devices that need less than that. A device that decodes more space than it uses need not respond to the unused space. Devices that map into I/O space must not use more than 256 bytes per Base Address Register. Use Memory Space if Possible Although PCI fully supports “I/O” space, the specification recom-mends that device registers be mapped into memory space if at all 105 PCI Bus Demystified possible. There are several reasons for this. In the PC architecture I/O space is limited and highly fragmented making it potentially difficult to allocate I/O space. Secondly, I/O space is assumed to have read side effects and is thus not prefetchable. This precludes certain opti-mizations that PCI-to-PCI bridges are allowed to perform. Finally, some processor architectures simply don’t support the notion of I/O address space. In practice, some devices use two Base Address Registers to repre-sent the same set of device registers. One of these BARs maps into memory space, the other into I/O space. Configuration software will allocate space to both registers if possible. Later when the device’s driver is invoked, it will decide, based on its environment and other considerations, which space to use. What is “Prefetchable”? Fundamentally, prefetchable memory space has no read “side effects.” This in turn means that the act of reading a memory location does not in any way change the contents. No matter how many times you read it, you get the same result. Conventional memory is pre-fetchable. A FIFO is not. Each time you read a FIFO you get the next data element. The primary objective in defining prefetchable memory is to allow PCI bridges to prefetch read data. In many cases prefetching can substantially reduce read latency. Consider a master agent exe-cuting a read to a location on the other side of a bridge. If the bridge recognizes that the location is prefetchable, it can go ahead and read subsequent locations (prefetch) on the assumption that the master intends to read further. If, on the other hand, the master chooses not to read further, no harm is done because the prefetch has not altered the contents of the prefetched registers. 106 ... - tailieumienphi.vn