the PCI Bus demystified phần 10

PCI Bus Demystified thus signaling its presence. When the HSC decides that it is appro-priate to apply backend power, it drives BD_SEL# low. HEALTHY# is an output from the board’s power isolation circuitry and is asserted when back end power is within tolerance (±5% according to the Compact PCI Specification). The assertion of HEALTHY# may also depend on other conditions being met, such as successfully completing a POST. This signal is not used on platforms without hardware connection control but all Hot Swap boards are required to implement it (see Figure 10-8). Platform / Board Platform / Board V/O HSC V/O V/O NC HEALTHY # Power Circuitry HEALTHY # Power Circuitry No Hardware Connection Control Hardware Connection Control Figure 10-8: Handling of the HEALTHY# signal. The HSC uses the assertion of HEALTHY# as the indication to deassert RST# to the board. Note that HEALTHY# may be deasserted at any time that the board determines it is not healthy. In response to seeing HEALTHY# deasserted, the HSC could notify the operating system of a faulty board and then attempt to isolate it by asserting RST# and deasserting BD_SEL#. The specification suggests a weak pullup on HEALTHY# so the signal is not floating in non-HA platforms. In a platform without hardware connection control, RST# is simply bussed to all slots and driven by the Host CPU in the system 184 Hot Plug and Hot Swap Platform / Board PCI_RST# HOST LOCAL_ PCI_RST# Platform / Board HOST PCI_RST# LOCAL_ PCI_RST# HEALTHY # HSC HEALTHY # No Hardware Connection Control Hardware Connection Control Figure 10-9: Handling of the RST# signal. slot. In HA platforms, RST# may be a radial signal from the HSC in which case it must be the OR of the system host’s reset and the slot-specific reset generated by the HSC. In any case, the board must keep its LOCAL_PCI_RST# asserted until HEALTHY# is asserted (see Figure 10-9). Summary The ability to change boards while the system is running is crucial to high-availability, mission-critical environments. Hot Plug, developed by the PCI SIG, and Hot Swap, developed by PICMG, provide solutions to this problem. Hot Plug places the burden of supporting live insertion on the platform so that virtually any PCI board is Hot Pluggable. Support for live insertion includes bus isolation and power switches on the motherboard for each slot. The operator must notify the system of his desire to insert or extract a board and wait for confirmation before taking the action. The Hot Plug Service provides the interface to the operator while the Hot Plug System Driver controls the platform resources. A set of Hot Plug primitives defines the essence of an API between these two elements. 185 PCI Bus Demystified Hot Swap builds on the Hot Plug model but places the burden of support on the board with only minor modifications to the back-plane. Hot Swap also includes a mechanism to automatically detect an insertion or extraction event, simplifying the operator’s task. The specification defines three models of Hot Swap operation: Basic. Operates much like Hot Plug. The operator must notify the system before taking any action. Full. Provides for automatic detection of insertion and extraction events. This allows the software connection process to proceed without operator intervention. High Availability. Adds software control of the hardware connection process. A board is taken out of reset and allowed to operate only after it has confirmed that it is “healthy.” 186 APPENDIX A Class Codes Class/ Subclass Class 00 00 01 Programming Interface Device predates class code definitions Non-VGA devices VGA devices Class 01 Mass storage controllers 00 SCSI controller 01 IDE controller xx See Note 1 02 Floppy disk controller 03 IPI bus controller 04 RAID controller Class 02 00 01 02 03 04 Class 03 00 01 02 Class 04 00 01 02 Network controllers Ethernet Token Ring FDDI ATM ISDN Display controllers VGA/8514 01 VGA-compatible 02 8514-compatible XGA 3-D controller Multimedia devices Video Audio Computer telephony Note 1. IDE Programming interface: Bit 0 Operating mode (primary) Bit 1 Programmable indicator (primary) Bit 2 Operating mode (secondary) Bit 3 Programmable indicator (secondary) Bit 7 Master IDE device 187 PCI Bus Demystified Class/ Subclass Class 05 00 01 Class 06 00 01 02 03 04 05 06 07 08 Class 07 00 01 02 03 Programming Interface Memory controllers RAM Flash Bridge devices Host bridge ISA bridge EISA bridge MCA bridge PCI to PCI bridge 00 PCI to PCI bridge 01 Supports subtractive decode PCMCIA bridge NuBus bridge Cardbus bridge RACEway bridge Simple communication controllers 00 Generic XT-compatible serial controller 01 16450-compatible serial controller 02 16550-compatible serial controller 03 16650-compatible serial controller 04 16750-compatible serial controller 05 16850-compatible serial controller 06 16950-compatible serial controller 00 Parallel Port 01 Bi-directional parallel port 02 ECP 1.X compliant parallel port 03 IEEE 1284 controller FE IEEE 1284 target device Multiport serial controller 00 Generic modem 01 Hayes compatible, 16450 interface (2) 02 Hayes compatible, 16550 interface (2) 03 Hayes compatible, 16650 interface (2) 04 Hayes compatible, 16750 interface (2) Note 2. First BAR (10h) maps appropriate compatible register set. Registers can be either memory or I/O mapped 188 ... - tailieumienphi.vn