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Chapter 15
Remote Sensing and High-Performance Reconfigurable Computing Systems
Esam El-Araby,
George Washington University
Mohamed Taher,
George Washington University
Tarek El-Ghazawi,
George Washington University
Jacqueline Le Moigne,
NASA’s Goddard Space Flight Center
Contents
15.1 Introduction .......................................................... 360 15.2 Reconfigurable Computing ............................................ 361 15.2.1 FPGAs and Reconfigurable Logic ............................. 361 15.2.2 Reconfigurable Computers .................................... 363
15.3 The Promise of Reconfigurable Computing for Remote Sensing ........ 364 15.4 Radiation-Hardened FPGAs ........................................... 365 15.5 Case Studies of Remote Sensing Applications ......................... 365
15.5.1 Wavelet-Based Dimension Reduction of Hyperspectral
Imagery ...................................................... 365 15.5.2 Cloud Detection .............................................. 368
15.5.2.1 ACCA Hardware Architecture ....................... 369 15.5.2.2 Normalization module ............................... 371 15.5.2.3 Pass-One Module .................................... 371 15.5.2.4 Detection Accuracy .................................. 372 15.5.2.5 Experimental Results ................................ 373
15.6 Summary and Observations ........................................... 375 References .................................................................. 376
The trend for remote sensing satellite missions has always been towards smaller size, lower cost, more flexibility, and higher computational power. On-board processing, asasolution,permitsagoodutilizationofexpensiveresources. Insteadofstoringand forwarding all captured images, data processing can be performed on-orbit prior to
359 © 2008 by Taylor & Francis Group, LLC
360 High-Performance Computing in Remote Sensing
downlink, resulting in the reduction of communication bandwidth as well as simpler and faster subsequent computations to be performed at ground stations. Reconfig-urable computers (RCs) combine the flexibility of traditional microprocessors with thepowerofFieldProgrammableGateArrays(FPGAs).Therefore,RCsareapromis-ing candidate for on-board preprocessing.
15.1 Introduction
The ability to preprocess and analyze remote sensing data onboard in real time can significantly reduce the amount of bandwidth and storage required in the production of space science products. Consequently, onboard processing can reduce the cost and the complexity of the On-the-Ground/Earth processing systems. Furthermore, it enables autonomous decisions to be taken onboard that can potentially reduce the delay between image capture, analysis, and action. This leads to faster critical decisions, which are crucial for future reconfigurable Web sensors missions as well as planetary exploration missions [1].
The new generation of remote sensing detectors produces enormous data rates. This requires a very high computing power to process the raw data, e.g., the onboard computer has to provide a performance of 3 × 1010 operations/second in space to process and classify hyperspectral raw data to get useful data [2]. Currently there is no space computer with such a performance.
Recently, Field Programmable Gate Array (FPGA) based computing, also known as ‘adaptive’ or ‘reconfigurable computing (RC),’ has become a viable target for the implementation of algorithms suited to image processing and computationally intensive applications. These computing systems combine the flexibility of general purpose processors with the speed of application-specific processors. By mapping hardware to FPGAs, the computer designer can optimize the hardware for a spe-cific application resulting in acceleration rates of several orders of magnitude over general-purpose computers. In addition, they are characterized by lower form/wrap factors compared to parallel platforms and higher flexibility than ASIC solutions. RC technology allows new hardware circuits to be uploaded via a radio link for physical upgrade or repair. Therefore, RCs are a promising candidate for onboard data prepro-cessing.High-speed,radiation-hardenedFPGAchipswithmilliongatedensitieshave recently emerged that can support the high throughput requirements for the remote sensing applications [3].
Figure 15.1 shows an example of onboard processing for hyperspectral images us-ing reconfigurable processing. Instead of storing and forwarding all captured images, dataprocessingcanbeperformedon-orbitpriortodownlink,resultinginthereduction of communication bandwidth as well as simpler and faster subsequent computations to be performed at ground stations.
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Remote Sensing and High-Performance Reconfigurable Computing Systems 361
Downlink
Reconfigurable Processor
Hyperspectral Imager
Figure 15.1 Onboard processing example.
15.2 Reconfigurable Computing
Applications have been traditionally implemented either in hardware using, for ex-ample, custom VLSI and Application-Specific Integrated Circuits (ASICs), or in software running on processors, such as Digital Signal Processors (DSPs), micro-controllers, and general-purpose microprocessors. These two extremes trade perfor-mance with flexibility, and vice versa. For example, ASICs are designed specifically to solve a given problem. Therefore, they are fast and efficient when compared with a microprocessor-based design. However, an ASIC circuit cannot be modified after fabrication. Due to their programmability, microprocessors offer more flexibility, but at the expense of speed.
Reconfigurable hardware [4] introduces a trade-off between traditional hardware and software by achieving hardware-like performance with software-like flexibility. Reconfigurable hardware offers the performance advantage of direct hardware exe-cution and the flexibility of software-like programming [5]. Figure 15.2 represents the trade-off between flexibility and performance for different implementation approaches.
15.2.1 FPGAs and Reconfigurable Logic
Reconfiguration in today’s reconfigurable computers is provided through FPGAs [6]. An FPGA can be viewed as programmable logic blocks embedded in programmable interconnects as shown in Figure 15.3. FPGAs are composed of three fundamental components: logic blocks, I/O blocks, and programmable interconnects. The logic blockisthebasicbuildingblockintheFPGA.InXilinx,whichiscurrentlythelargest FPGA vendor, this logic block is called a Configurable Logic Block (CLB). Routing resources enable efficient communication among CLBs. The CLB usually consists of lookup tables (LUTs), carry logic, flip-flops, and programmable multiplexers, as shown in Figure 15.4. The device can be programmed using a hardware description language such as VHDL, or using schematic capture software. There are also many C-to-gatescompilersfromresearchgroupsandfromcommercialvendors.Acircuitis
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362 High-Performance Computing in Remote Sensing
Programmability/Flexibility
GPPs
General Purpose Processor
Programmable DSP
Re-configurable Hardware
ASICs
Performance
Figure 15.2 Trade-off between flexibility and performance [5].
implementedinanFPGAbyprogrammingeachlogicblocktorealizeaportionofthe logic required by the circuit, and each of the I/O blocks to act as either an input pad or an output pad, as required by the circuit. The programmable routing is configured to make all the necessary connections among the logic blocks and between logic blocks and I/O blocks. The programming technology determines the method of storing the configuration information.
I/O Block
Logic Block
Interconnected Resources
Figure 15.3 FPGA structure.
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Remote Sensing and High-Performance Reconfigurable Computing Systems 363
COUT
G4 G3 G2 G1
F5IN
BY SR
F4 F3 F2
F1
Look-UP Table
Look-Up Table O
YB
Y
Carry & Control Logic
XB
X
Carry & Control Logic
S
D Q
CK
EC
R
S
D Q
CK
EC
R
CIN CLK
CE SLICE
Figure 15.4 CLB structure.
15.2.2 Reconfigurable Computers
Reconfigurable computers [4, 7, 8, 9] are composed of one or more general-purpose processors and one or more reconfigurable chips, such as Field Programmable Gate Arrays(FPGAs)closelyintegratedwitheachother.Theprocessorperformstheopera-tionsthatcannotbedoneefficientlyinthereconfigurablelogic,suchasdata-dependent control (e.g., loops and branches) and possibly memory accesses, while the compu-tational cores are mapped to the reconfigurable hardware. Reconfigurable computing systems can be based on commodity PC boards (such as Pentium boards), where the reconfigurable processor sub-system is typically a commercial, off-the-shelf (COTS) FPGA accelerator board, such as WildStar II [10]. The reconfigurable board acts as a co-processor to the PC or workstation processor. Usually, they are interfaced to a computer via a PCI bus. RCs have recently evolved from accelerator boards to stand-alone general-purpose RCs and parallel reconfigurable supercomputers. Examples of such supercomputers are the Cray-XD1, SRC-6, and the SGI-Altix with FPGA bricks. These systems can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of pro-grammabilityasgeneral-purposecomputers.Atypicalreconfigurablecomputernode
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