Development of the parallel BCH and LDPC encoders architecture for the second generation digital video broadcasting standards with adjustable encoding parameters on FPGA
Development of the parallel BCH and LDPC encoders architecture for the second generation digital video broadcasting standards with adjustable encoding parameters on FPGA
This paper proposes a new approach to parallel implementation of BCH and LDPC encoders with adjustable encoding parameters, supporting all the different BCH + LDPC code configurations. The proposed solution is fully backward compatible to legacy decoder on the receiving side.