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Analog and Interface Guide – Volume 1
A Compilation of Technical Articles and Design Notes
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Table of Contents
Contents
An Intuitive Approach To Mixed Signal Layout
Part 1 – The Art Of Laying Out Two Layer Boards ....................................................................................1
Part 2 – Could It Be Possible That Analog Layout Differs From Digital Layout Techniques? .........................5
Part 3 – Where the Board and Component Parasitics Can Do The Most Damage.......................................8
Part 4 – Layout Techniques To Use As The ADC Accuracy And Resolution Increases ................................11
Part 5 – The Trouble With Troubleshooting Your Layout Without The Right Tools.......................................13
Part 6 – Layout Tricks For A 12-Bit Sensing System ..............................................................................15
Miscellaneous
Keeping Power Hungry Circuits Under Thermal Control ..........................................................................19
Instrumentation Electronics At A Juncture ............................................................................................21
Select The Right Operational Amplifier For Your Filtering Circuits ............................................................23
Ease Into The Flexible CANbus Network ...............................................................................................25
All articles presented here are authored by Bonnie C. Baker, Mixed Signal/Analog Applications Manager, Microchip Technology Inc.
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An Intuitive Approach to Mixed Signal Layout – Part 1
The Art of Laying Out Two Layer Boards
In this highly competitive, battery-powered marketplace, cost
objective usually dictates that a designer uses two layer boards
in the design. Although the multi-layer board (4-, 6- and 8-layers)
allows the designer to build cleaner solutions in terms of size,
noise and performance, financial pressures force the engineer to
rethink his layout strategies with the two-layer board in mind. In
this article we will discuss the use or misuse of auto routing, the
concept of current return paths with and without ground planes,
and recommendations for component placement where two layer
boards are concerned.
Pay Now Or Pay Later With The Auto
Router And Analog Circuits
It is tempting to use the auto router when designing a printed
circuit board (PCB). More often than not, a purely digital board,
(especially if the signals are relatively slow, and the circuit
density is low) will work just fine. But as you try to lay out analog,
mixed signal or high-speed circuits with the auto routing tool that
is available with your layout software there may be some issues.
The probability of creating serious circuit performance problems
is very real.
Figure 1: Top layer of an auto-routed layout of circuit diagram
For instance, the auto routed top layer of a two-layer board is shown in Figure 3.
shown in Figure 1. The bottom layer of this board is in Figure 2,
and the circuit diagram for these layout layers is in Figure 3a and
Figure 3b. For the layout of this mixed-signal circuit, the devices
were manually placed on the board with careful thought to
separating the digital and analog devices.
With this layout there are several areas of concern, but the
most troubling issue is the grounding strategy. If the ground
traces are followed on the top layer, every device is connected
through traces on that layer. A second ground connection for
every device uses the bottom layer with vias at the far right-
hand side of the board. The immediate red flag that one should
see when examining this layout strategy would be the existence
of several ground loops. Additionally, the ground return paths
on the bottom side are interrupted with horizontal signal lines.
The saving grace with this grounding scheme is that the analog
devices (MCP3202, 12-bit A/D converter and MCP4125, 2.5V
voltage reference) are at the far right hand side of the board. This
placement ensures that digital ground signals do not pass under
these analog chips.
Figure 2: Bottom layer of an auto-routed layout of circuit
diagram shown in Figure 3.
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An Intuitive Approach to Mixed Signal Layout – Part 1
The manual layout of the circuit shown, in Figure 3a and Figure
3b, is given in Figure 4 and Figure 5. With this manual layout, a
few general guidelines are followed to ensure positive results.
These guidelines are:
1. Use the ground plane as a current return path as much as
possible.
2. Separate the analog ground plane from the digital ground
plane with a break.
3. If interruptions from signal traces are required on the
ground-plane side, make them vertical to reduce the
interference with the ground current return paths.
4. Place analog circuitry at the far end of the board and digital
circuitry closest to the power connects. This reduces the Figure 3b: Analog section of circuit diagram for layouts in Figures
effects of di/dt from digital switching. 1, 2, 4 and 5. This is the circuit diagram from Microchip’s MXDEV®
evaluation board for the 10- and 12-bit ADCs (MCP300X and
MCP320X).
Note that with both of these two layer boards there is a ground
plane on the bottom. This is only done so that an engineer
working on the board can quickly see the layout when trouble
shooting. This strategy is typically found with a manufacturer’s
demo and evaluation boards. But more typically, the ground
plane is on the top of board, thereby reducing electromagnetic
interference (EMI).
Figure 4: Top layer of a manual routed layout of circuit diagram
shown in Figure 3.
Figure 3a: Circuit diagram for layouts in Figures 1, 2, 4 and 5. This
is the circuit diagram from Microchip’s MXDEV® evaluation board
for the 10- and 12-bit ADCs (MCP300X and MCP320X).
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An Intuitive Approach to Mixed Signal Layout – Part 1
Figure 6: If a ground plane is not feasible, current return paths
Figure 5: Bottom layer of a manual routed layout of circuit
can be handled with a “star” layout strategy.
diagram shown in Figure 3.
4. Digital currents should not pass across analog devices.
Current Return Paths With Or Without A Ground Plane
During switching, digital currents in the return path are
The fundamental issues that should be considered when dealing
fairly large, but only briefly. This phenomenon occurs due
with current return paths are:
to the effective inductance and resistance of the ground.
1. If traces are used, they should be as wide as possible. In
With the inductance portion of the ground plane or trace,
the event that you are considering using traces for your
the governing formula is V = Ldi/dt, where V is the resulting
ground connects on your PCB, they should be designed to
voltage, L is the inductance of the ground plane or trace, di
be as wide as possible. This is a good rule of thumb, but
is the change in current from the digital device and dt is the
also understand that the thinnest width in your ground trace
time span considered for the event. To calculate the effects
will be the effective width of the trace from that point to the
of the resistance portion of the ground plane, changes in the
end, where the “end” is defined as the point furthest from the
voltage simply change because of V = RI, again where V is the
power connection.
resulting voltage, R is the ground plane or trace resistance
2. Ground loops should be avoided. and I is the current change caused by the digital device. These
3. If no ground plane is available, star connection strategies changes in the voltage of the ground plane or trace across the
should be used. analog device will change the relationship between ground and
the signal in the signal chain.
A graphical example of a star connection strategy is shown in
Figure 6. 5. High-speed current should not pass across lower speed
devices.
With this type of approach, the ground currents return to the
power connection independently. You will note that in Figure 6 all Ground-return signals of high-speed circuits have a
of the devices do not have their own return path. With U1 and similar effect on changes to the ground plane. Again the
U2, the return path is shared. This can be done if guidelines 4 more important formulas that determine the effects of
and 5 are used. this interference are V = Ldi/dt for the ground plane or
trace inductance and V = RI for the ground plane or trace
resistance. And as with digital currents, high-speed circuits
that ground activity on the ground plane or that trace across
the analog device change the relationship between ground
and the signal in the signal chain.
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An Intuitive Approach to Mixed Signal Layout – Part 1
Conclusion
6. Regardless of the technique used, the ground return paths
must be designed to have a minimum resistance and At every layout-related presentation that I give in a seminar
inductance. setting, the question always asked in one form or another is,
7. If a ground plane is used, breaks in plane can improve or “What if management tells me I can’t have two layers or a ground
degrade circuit performance. Use with care. plane, and I still need to reduce noise in the circuit? How do I
design my circuit to work around the need for a ground plane?”
A clean way of separating analog and digital ground planes is
Typically, I instruct the person asking the question to inform their
shown in Figure 7.
management that a ground plane is simply required if they want
In Figure 7, the precision analog is closer to the connector,
reliable circuit performance. The primary reason for using ground
however it is isolated from the activity in the digital network as
planes is lower ground impedance. They also provide a degree of
well as the switching currents from the power supply circuit.
EMI reduction.
This is a very effective way of keeping the ground return paths
But, if you are unable to win that battle because of cost
separated. This technique was also used in the layout previously
constraints, this article offers some suggestions such as star
discussed in Figure 4 and 5.
networks and current return paths which if used properly will give
a little relief with the circuit noise.
Figure 7: Sometimes a continuous ground plane is less effective than if the ground plane was separated. In this Figure (a) shows a less
desirable grounding layout strategy than is shown in (b).
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An Intuitive Approach to Mixed Signal Layout – Part 2
Could It Be Possible That Analog Layout Differs
From Digital Layout Techniques?
The increasing percentage of digital designers and digital layout For digital devices, such as controllers and processors,
experts in the engineering population reflects the directions that decoupling capacitors are required, but for a different reason.
our industry is headed. Although the emphasis on digital design One of the functions of these capacitors serves as a “mini”
is providing significant advances in electronics end products, charge reservoir. Frequently in digital circuits, a great deal of
there is still and will always be a portion of circuit design current is required to execute the transitions of the changing
that interfaces with the analog or real world. There is some gate states. Because of the switching transient currents that
similarity in layout strategies between these two domains, but occur on the chip and throughout the circuit board, having
the differences can make an easy circuit layout design less than additional charge “on call” is advantageous. The consequence
optimum when trying to achieve good results. In this article, we of not having enough charge locally to execute this switching
will discuss the fundamental similarities and differences between action could result in a significant change in the power supply
analog and digital layout with respect to bypass capacitors, power voltage. When the voltage change is too large, it will cause the
supply and ground layout, voltage errors, and electromagnetic digital signal level to go into the indeterminate state, more than
interference (EMI) due to PCB layout. likely resulting in erroneous operation of the state machines
in the digital device. The switching current passing through the
The Similarities Of Analog And circuit board traces would cause this change in voltage. The
Digital Layout Practices circuit board traces have parasitic inductance, and the change in
voltage results can be calculated using the formula:
Bypass Or Decoupling Capacitors
V = LdI/dt
In terms of layout, analog devices and digital devices all require
these types of capacitors. In both cases, these devices require Where: V = voltage change
a capacitor as close to the power supply pin(s) with a common L = board trace inductance
value for this capacitor of 0.1 micro-farads (μF). A second class dI = change in current through the trace
of capacitor in the system is required at the power supply source.
dt = the time it takes for the current to change
The value of this capacitor is usually about 10 μF.
So for multiple reasons, it is a good idea to bypass (or decouple)
The position of these capacitors is shown in Figure 1. The values
the power supply at the power supply and at the power supply pin
of these capacitors can vary by being ten times higher or lower,
of active devices.
but they are both required to have short leads and be as close
to the devices (in the case with the 0.1 μF capacitor) or power The Power And Ground Should Be Routed Together
supply source (in the case with the 10 μF capacitor) as possible. When power and ground traces are well matched with respect
Bypass or decoupling capacitors and their placement on the to location, the opportunities for EMI is lessened. If power
board are just common sense for both types of designs, but and ground are not matched, system loops are designed into
interesting enough, for different reasons. In the analog layout the layout and the possibility of seeing “noisy” results without
design, bypass capacitors generally serve the purpose of explanation is possible. An example of a PCB designed with the
redirecting high frequency signals on the power supply that would power and ground traces not matched is shown in Figure 2.
otherwise enter into the sensitive analog chip through the power The loop area that is designed into this board is 697cm2. The
supply pin. Generally speaking, these high frequency signals opportunity for induced voltages in the loop because of radiated
occur at frequencies beyond the analog device’s capability to noise off the board and in the board is decreased dramatically
reject those signals. The possible consequences of not using a using the approach shown in Figure 3.
bypass capacitor in your analog circuit results in the addition of
undue noise to the signal path and worse yet, oscillation.
Figure 1: In analog and digital PCB design, the bypass or decouple
capacitors (1 μF) should be positioned as close to the device as Figure 2: The power and ground traces are laid out using different
possible. The power supply decoupling capacitor (10 μF) should routes to the device on this board. This mismatch opens the
be positioned where the power bus enters the board. In all cases, opportunity for EMI into the electronics of this board.
these capacitors should have short leads.
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An Intuitive Approach to Mixed Signal Layout – Part 2
Location of Components
In every PCB design, the noisy and quiet portions of the circuit
should be separated as mentioned above. Generally speaking,
the digital circuitry is “rich” with noise and in turn less sensitive
to this type of noise (because of the larger voltage noise
margins). In contrast the voltage noise margins of the analog
circuitry are much smaller. Of the two domains, the analog
domain is most sensitive to switching noise. In the layout of a
mixed signal system, the two domains should be separated. This
is graphically shown in Figure 4.
Parasitics Designed Into The PCB
There are two fundamental parasitic components that can easily
be designed into the PCB that might create problems; a capacitor
and an inductor. A capacitor is designed into a board simply
by placing two traces close to each other. This can be done by
placing the two traces, one on top of the other with two layers or
Figure 3: In this one layer board, the power trace and ground trace by placing them beside each other on the same layer, as shown
are laid next to each other on their way to the device on this board. in Figure 5. In both trace configurations, changes in voltage with
This board is better matched than that shown in Figure 2. The time (dV/dt) on one trace could generate a current on a second
opportunity for EMI into the electronics of this board is lessened by trace. If the second trace is high impedance, the current that is
679/12.8 or ~54x. created by the e-field of this event will convert into a voltage.
Fast voltage transients are most typically found on the digital
Where The Domains Differ side of the mixed signal design. If the traces that have these
Ground Planes Can Be A Problem fast voltage transients are in close proximity of high impedance
analog traces, this type of error will be very disruptive with analog
The fundamentals of circuit board layout apply to analog circuits
circuitry accuracy. Analog circuitry has two strikes against it in
as well as digital circuits. One fundamental rule of thumb is to
this environment. The noise margins are much lower than digital
use uninterrupted ground planes. This common practice reduces
and it is not unusual to have high impedance traces.
the effects of dI/dt (change in current with time) in digital
circuits, which changes the potential of ground and noise being This type of phenomena can be easily minimized using one of
injected into the analog circuits. But when comparing digital and two techniques. The most commonly used technique is to change
analog circuits, the layout techniques are essentially the same the dimensions between the traces as the capacitor equation
with one exception. The added precaution that should be taken suggests. The most effect dimension to change is the distance
with analog circuits is to keep the digital signal lines and return between the two offending traces. It should be noted that the
paths in the ground plane as far away from the analog circuitry variable, “d”, is in the denominator of the capacitor equation. As
as possible. This can be done by connecting the analog ground “d” is increased, the capacitance will decrease. Another variable
plane separately to the system ground connect or having the that can be changed is the length of the two traces. In this case,
analog circuitry at the farthest side of the board, i.e., at the end if the length (“L”) is reduced the capacitance between the two
of the line. This is done in order to maintain signal paths that traces will also be reduced.
have a minimal amount of interference from external sources. Another technique used is the lay a ground trace between the
The opposite is not true for digital circuitry. The digital circuitry two offending traces. Not only is the ground trace low impedance,
can tolerate a great deal of noise on the ground plane before but an additional trace like this will break up the e-fields that are
problems start to appear. causing the disturbance shown in Figure 5.
a) Separate the Digital and b) High Frequency Components
Analog Portions of Should be Placed Near
the Circuit the Connectors
high
frequency
low
Figure 4: If possible, (a) the digital and analog portion of circuits should be separated in order to separate the digital switching activity from
the analog circuitry. Additionally, (b) the high frequency should be separated from the low frequency where possible, keeping the higher
frequency components closer to the board connector.
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An Intuitive Approach to Mixed Signal Layout – Part 2
w = thickness of PCB trace
L = length of PCB trace
w • L • eo • er d = distance between the two PCB traces
C= pF
dielectric constant of air = 8.85 x 10-12 F/m
d eo =
er = dielectric constant of substrate coating relative to air
Guard Trace
Voltage IN
Coupled
Current
I = C dV (amps)
dt
Figure 5: Capacitors can easily be fabricated into a PCB by laying out two traces in close proximity. With this type of capacitor, fast voltage
changes on one trace can initiate a current signal in the other trace.
The way that an inductor is designed into a board is similar to
the construction of a capacitor. Again this is done by placing two Voltage
traces, one on top of the other with two layers or by placing them Current IN
beside each other on the same layer, as shown in Figure 6. In
L M L
both trace configurations, changes in current with time (dI/dt)
on one trace could generate a voltage in the same trace due to
the inductance on that trace and initiate a proportional current dl
V=L (volts)
on the second trace due to the mutual inductance. If the voltage dt
change is high enough on the primary trace, the disturbance can
L = x (0.01) In(1+2π h/w) uH/in
reduce the voltage margin of the digital circuitry enough to cause
M = x (0.01) In(1+2π h/w) uH/in
errors. This phenomena is not necessary reserved for digital
circuits, but more common in that environment because of the
larger, seemingly instantaneous switching currents.
Signal Trace
To eliminate potential noise for EMI sources it is best to separate
quiet analog lines versus noisy I/O ports. Try to implement low
impedance power and ground networks, minimize inductance in Current Return Path
conductors for digital circuits and minimize capacitive coupling in
analog circuits.
Conclusion
When the domains meet, careful layout is critical if a designer
Figure 6: If little attention is paid to the placement of traces, line
intends to have a successful final PCB implementation. Layout
inductance and mutual inductance can be created with the traces
strategies usually are presented as rules of thumb because
in a PCB. This kind of parasitic element is most detrimental to the
it is difficult to test the success of your final product in a lab
circuit operation where digital switching circuits reside.
environment. So, generally speaking, although there are some
similarity in layout strategies between the digital and analog
domain, the differences should be recognized and worked with.
In this article we briefly talked about bypass capacitors, power
supply and ground layout, voltage errors and EMI because of PCB
layout.
For more information refer to:
[1] Henry W. Ott, Noise Reduction Techniques in Electronic
Systems, 2nd ed., Wiley, 1998
[2] Ralph Morrison, Noise and Other Interfering Signals, Wiley and
Sons, 1992
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An Intuitive Approach to Mixed Signal Layout – Part 3
Where The Board And Component
Parasitics Can Do the Most Damage
The major classes of parasitics generated by the PC board To quickly explain the circuit operation in Figure 2, a 16-bit
layout come in the form of resistors, capacitors and inductors. DAC is built using three 8-bit digital potentiometers and three
For instance, PCB resistors are formed as a result of traces CMOS operational amplifiers. To the left side of this figure, two
from component to component. Unintentional capacitors can digital potentiometers (U3a and U3b) span across VDD to ground
be built into the board with traces, soldering pads and parallel with the wiper output connected to the non-inverting input of
traces. Circumstances that surround where inductors are built two amplifiers (U4a and U4b). The digital potentiometers, U2
come in the form of loop inductance, mutual inductance and and U3 are programmed using an SPI™ interface between
vias. All of these parasitics stand a chance of interfering with the microcontroller, U1. In this configuration, each digital
the effectiveness of your circuit as you transition from the circuit potentiometer is configured to operate as an 8-bit multiplying
diagram to the actual PCB. This article quantifies the most DAC. If VDD is equal to 5V, the LSB size of these DACs is equal to
troublesome class of board parasitics, the board capacitor, and 19.61 mV.
gives an example of where the effects on circuit performance can The wipers of each of these two digital potentiometers are
be clearly seen. connected to the non-inverting inputs of two buffer configured
operational amplifiers. In this configuration, the inputs to
Feeling the Pain of Those Unnecessary Capacitors
the amplifiers are high impedance, which isolates the digital
In Part 2 of this series we discussed how capacitors could potentiometers from the rest of the circuit. These two amplifiers
inadvertently be built into your board. To quickly review this are also configured so that the output swing restrictions on the
concept, most layout capacitors are built by placing two parallel amplifiers in the second stage are not violated.
traces close together. The value of this type of capacitor can be
To have this circuit perform as a 16-bit DAC (U2a), a third digital
calculated using the formulas shown in Figure 1 (note that this
potentiometer spans across the output of these two amplifiers,
figure is the same as Figure 5 in Part 2 of this series).
U4a and U4b. The programmed setting of U3a and U3b sets the
This type of capacitor can cause problems in mixed signal voltage across the digital potentiometer. Again, if VDD is 5V
circuits where sensitive, high impedance analog traces are in it is possible to program the output of U3a and U3b 19.61 mV
close proximity to digital traces. For example, the circuit in apart. With this size of voltage across the third 8-bit digital
Figure 2 has the potential to have this type of problem. potentiometer, R3, the LSB size of this circuit from left to right is
76.3 mV. The critical device specifications that will give optimum
performance with this circuit are given in Table 1.
w = thickness of PCB trace
L = length of PCB trace
w • L • eo • er d = distance between the two PCB traces
C= pF
dielectric constant of air = 8.85 x 10-12 F/m
d eo =
er = dielectric constant of substrate coating relative to air
Guard Trace
Voltage IN
Coupled
Current
I = C dV (amps)
dt
Figure 1: Capacitors can easily be fabricated into a PCB by laying out two traces in close proximity. With this type of capacitor, fast voltage
changes on one trace can initiate a current signal in the other trace. (Also found in Part 2, Could It Be Possible That Analog Layout Differs
From Digital Layout Techniques, Figure 5.)
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An Intuitive Approach to Mixed Signal Layout – Part 3
Figure 2: A 16-bit DAC can be built using three 8-bit digital potentiometers and three amplifiers to provide 65,536 different output
voltages. If VDD is 5V in this system the resolution or LSB size of this DAC is 76.3 mV.
This circuit can be used in two basic modes of operation. The The first pass layout of the circuit in Figure 2 is shown in Figure
first mode would be if you wanted a programmable, adjustable, 3. This circuit was quickly designed in our lab without attention
DC reference. In this mode the digital portion of the circuit is to detail. The consequences of placing digital traces next to high
only used occasionally and certainly not during normal operation. impedance analog lines were overlooked in the layout review.
The second mode would be if you used the circuit as an arbitrary This speaks strongly to doing it right the first time, but to our
wave generator. In this mode, the digital portion of the circuit is benefit this article will illustrate how to identify the problem and
an intimate part of the circuit operation. In this mode, the risk of make significant improvements.
capacitive coupling may occur.
Device Specification Purpose
Digital Potentiometers Number of bits 8-bits Determines the overall LSB size and resolution of the
(MCP42010) circuit.
Nominal resistance 10 kΩ (typ) The lower this resistance is the lower the noise
(resistive element) contribution will be to the overall circuit. The trade off is
that the current consumption of the circuit is high with
these lower resistances.
DNL ± 1 LSB (max) Good Differential Non-Linearity is needed to insure no
missing codes occur in this circuit which allows for a
possible 16-bit operation.
9 nV / √Hz
Voltage Noise Density If the noise contribution of these devices is too high it
(for half of the resistive will take away from the ability to get 16-bit noise free
@ 1 kHz (typ)
element) performance. Selecting lower resistive elements can
reduce the digital potentiometer noise.
Operational Amplifiers Input Bias Current, IB 1 pA @ 25°C (max) Higher IB will cause a DC error across the potentiometer.
(MCP6022) CMOS amplifiers were chosen for this circuit for that
reason.
Input Offset Voltage 500 mV (max) A difference in amplifier offset error between A1 and A2
could compromise the DNL of the overall system.
8.7 nV / √Hz
Voltage Noise Density If the noise contribution of these devices is too high
it will take away from the ability to get 16-bit accurate
@10 kHz (typ)
performance. Selecting lower noise amplifiers can reduce
amplifier noise.
Table 1: From the long list of specifications that each of the devices has, there are a handful of key specifications that make this
circuit more successful when it is used to provide DC reference voltages or arbitrary wave forms.
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An Intuitive Approach to Mixed Signal Layout – Part 3
What is the solution to this problem? Basically we separated the
traces. Figure 5 shows an improved layout solution.
The results of the layout change are shown in Figure 6. With
the analog and digital traces carefully kept apart, this circuit
becomes a very clean 16-bit DAC. A single code transition of the
third digital potentiometer 76.29 mV is shown with the green
trace. You may notice that the oscilloscope scale is
80 mV/div and that the amplitude of this code change is shown
to be approximately 80 mV. In the lab, we were forced by the
equipment to gain the output of the 16-bit DAC by 1000x.
Figure 3: This is the first attempt at the layout for the circuit
in Figure 2. In this figure it can quickly be seen that a critical
high impedance analog line is very close to a digital trace. This
configuration produces inconsistent noise on the analog line
because the data input code on that particular digital trace
changes, dependent on the programming requirements for the
digital potentiometer.
Taking a look at the color-coding in this layout it is obvious where
a potential problem is. The analog trace (blue) that is pointed out
goes from the wiper of U3a to the high impedance amplifier input
of U4a. The digital trace (green) that is pointed out carries the Figure 5: With this new layout the analog lines have been
digital word that programs the digital potentiometer settings. separated from the digital lines. This distance has essentially
eliminated the digital noise that was causing interference in the
On the bench, it is found that the digital signal on the green trace
previous layout.
is coupled into the sensitive blue trace. This is illustrated in the
scope photo below (Figure 4).
The digital signal that is programming the digital potentiometers
in the system has transmitted from trace to trace onto an analog
line that is being held at a DC voltage. This noise propagates
through the analog portion of the circuit all the way out to the
third digital potentiometer (U5a). The third digital potentiometer
is toggling between two output states.
Figure 6: The 16-bit DAC in this new layout is showing a single
code transition with no digital noise from the communication to
the digital potentiometers.
Conclusion
Once again, when the digital and analog domains meet, careful
Figure 4: In this scope photo, the top trace was taken at JP1 layout is critical if you intend to have a successful final PCB
(digital word to the digital potentiometers), the second trace on implementation. In particular, active digital traces close to high
JP5 (noise on the adjacent analog trace) and the bottom yellow impedance analog traces will cause serious coupling noise that
trace is taken at -TP10 (noise at the output of the 16-bit DAC). can only be avoided with distance between traces.
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An Intuitive Approach to Mixed Signal Layout – Part 4
Layout Techniques To Use As The
ADC Accuracy and Resolution Increase
Initially, analog-to-digital (A/D) converters rose from an analog These types of converters can have several pins for the ground
paradigm where a large percentage of the physical silicon was and power connections. The pin names are often misleading in
analog. As the progression of new design topologies evolves, that the analog and digital connections can be differentiated with
this paradigm shifted to where slower speed A/D converters the pin label. These labels are not meant to describe the system
were predominately digital. Even with this on-chip shift from connections to the PCB, but rather they identify how the digital
analog to digital, the PCB layout practices have not changed. and analog currents come off the chip. Knowing this information
Now as always, when the layout designer is working with mixed and understanding that the primary real estate consumed on the
signal circuits, key layout knowledge is still needed in order to chip is analog, it makes sense to connect the power and ground
implement an effective layout. This article will look at the PCB pins on the same planes, e.g., analog planes.
layout strategies required for A/D converters using successive For instance, the pinout for a representative sample of 10-bit and
approximation register (SAR) and Sigma-Delta topologies. 12-bit converters are shown in Figure 2.
SAR Converter Layout With these devices, the ground is usually directed off the
chip with two pins: AGND and DGND. The power is taken for
SAR A/D converters can be found with 8-bit, 10-bit, 12-bit, 16-
a single pin. When implementing the PCB layout using these
bit and sometimes 18-bit resolution. Originally, the process and
chips, the AGND and DGND should be connected to the analog
architecture for these converters was bipolar with R-2R ladders.
ground plane. The analog and digital power pins should also be
But recently these devices have migrated to a CMOS process
connected to the analog power plane or at least connected to
with a capacitive charge distribution topology. Needless to say,
the analog power train with proper by-pass capacitors as close to
the system layout strategy for these converters has not changed
each pin as possible. The only reason that these devices would
with this migration. The basic approach to layout is consistent
have only one ground pin and one positive supply pin, as with the
except for higher resolution devices. These devices require more
MCP3201, is due to package pin limitations. However, separate
attention to the prevention digital feedback from the serial or
grounds enhance the probability of getting good and repeatable
parallel output interface of the converter.
accuracy from the converter.
The SAR converter is predominately analog in terms of circuitry
With all of the converters, the power supply strategy should
and the amount of real estate dedicated to the different domains
be to connect all grounds, positive supply and negative supply
on the chip. In Figure 1, a block diagram of a 12-bit CMOS SAR
pins to the analog plane. In addition, the ‘COM’ pin or ‘IN’ pin
converter is shown.
associated with the input signal should be connected as close to
Within this block diagram the Sample/Hold, comparator, most the signal ground as possible.
of the digital-to-convert (DAC) and 12-bit SAR are analog. The
remaining portions of the circuit are digital. As a consequence,
most of the power and current needed for this converter is used
for the internal analog circuitry. There is very little digital currents
coming from the device with the exception of the small amount of
switching that occurs in the DAC and at the digital interface.
Figure 2: The SAR converter, regardless of resolution, usually has
at least two ground connects: AGND and DGND. The converters
illustrated here are the MCP3201 and MCP3008 from Microchip.
Figure 1: A block diagram of a 12-bit CMOS SAR A/D converter.
This converter uses a charge distribution across a capacitive array.
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An Intuitive Approach to Mixed Signal Layout – Part 4
Precision Sigma-Delta Layout Strategies
Higher resolution SAR converters (16- and 18-bit converters)
require a little more consideration in terms of separating The silicon area of the precision Sigma-Delta A/D converter
the digital noise from the quiet analog converter and power is predominately digital. In the early days, when this type
planes. When these devices are interfaced to a microcontroller, of converter was being produced, this shift in the paradigm
external digital buffers should be used in order to achieve clean prompted users to separate the digital noise from the analog
operation. Although these types of SAR converters typically have noise by using the PCB planes. As with the SAR A/D Converter,
internal double buffers at the digital output, external buffers these types of A/D converters can have multiple analog- and
are used to further isolate the digital bus noise from the analog digital ground and power pins. Once again, the common tendency
circuitry in the converter. An appropriate power strategy for this of a digital or analog design engineer is to try separating these
type of system is shown in Figure 3. pins into separate planes.
Unfortunately, this tendency is misguided, particularly if you
intend to solve critical noise problems with the 16-bit to 24-bit
accuracy devices.
With high-resolution Sigma-Delta converters that have a 10 Hz
data rate, the clock (internal or external) to the converter could
be as high as 10 MHz or 20 MHz. This high frequency clock is
used for switching the modulator and running the oversampling
engine. With these circuits, the AGND and DGND pins are
connected together on the same ground plane, as is the case
with the SAR converter. Additionally, the analog and digital power
pins are connected together, preferably on the same plane. The
requirements on the analog and digital power planes are the
same as with the high-resolution SAR converters.
A ground plane is mandatory, which implies that a double-sided
board is needed at minimum. On this double-sided board,
the ground plane should cover at least 75% of the area if not
more. The purpose of this ground plane layer is to reduce
grounding resistance and inductance as well as provide a shield
against electro-magnetic interference (EMI) and radio-frequency
interference (RFI). If circuit interconnect traces need to be put on
the ground-plane side of the board, they should be as short as
possible and perpendicular to the ground current return paths.
Conclusion
You can get away without separating the analog and digital pins
of low precision A/D converters, such as 6-, 8- or maybe even
10-bit converters. But as the resolution/accuracy increases with
your converter selection, the layout requirements also become
Figure 3: With high-resolution SAR A/D converters, the converter more stringent. In both cases, with high resolution SAR A/D
power and ground should be connected to the analog planes. The converters and Sigma-Delta converters these devices need to be
digital output of the A/D converter should then be buffered, using connected directly to the lower noise analog ground and power
external 3-state output buffers. These buffers provide isolation planes.
between the analog and digital side, in addition to high-drive
capability.
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An Intuitive Approach to Mixed Signal Layout – Part 5
The Trouble With Troubleshooting Your Layout
Without The Right Tools
When you’re trying to solve a signal integrity problem, the best of Further investigations into the circuit shows that the source of
all worlds is to have more than one tool to examine the behavior the noise seen on the time plot comes from the switching power
of a system. If there is an A/D converter in the signal path, there supply. An inductive choke is added to the circuit along with
are three fundamental issues that can easily be examined when bypass capacitors. One 10 μF is positioned at the power supply
assessing the circuit’s performance. All three of these methods and three 0.1 μF capacitors are placed as close to the supply
evaluate the conversion process as well as its interaction with pins of the active elements as possible. Now the generation of
the layout and other portions of the circuit. The three areas of a new time plot seems to produce a solid DC output and this
concern encompass the use of frequency analysis (FFTs), time is verified with the Histogram results, shown in Figure 3. The
analysis, and DC analysis techniques. This article will explore the data shows these changes eliminated the noise source from the
use of these tools to identify the source of problems as it relates signal path of the circuit.
to the layout implementation of circuits. We will explore how you
decide what to look for, where to look, how to verify problems
through testing and how to solve the problems that are identified.
The circuit that was built and is used in the following discussion
is shown in Figure 1.
Power Supply Noise
A common source of interference in circuit applications is from
the power supply. This interference signal is typically injected
through the power supply pins of the active devices. For instance,
a time based plot of the output of the A/D converter in Figure 1
is given in Figure 2. In this figure, the sample speed for the A/D
converter was 40 ksps and 4096 samples were taken.
In this case, the instrumentation amplifier, voltage reference
and A/D converter do not have by-pass capacitors installed.
Additionally, the inputs to the circuit are both referenced to a low
noise, DC voltage source of 2.5V.
Figure 2: The time domain representation of this data from the
3201, 12-bit A/D converter produces an interesting periodic signal.
This signal source was traced back to the power supply.
Figure 1: The voltage at the output of the SCX015 pressure sensor is gained by the instrumentation amplifier (A1 and A2). Following the
instrumentation amplifier a low pass filter (A3) is inserted to eliminate aliased noise from the 12-bit A/D converter conversion.
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An Intuitive Approach to Mixed Signal Layout – Part 5
Improper Use of Amplifiers
Returning to the circuit shown in Figure 1, a 1 kHz AC signal is
injected at the positive input to the instrumentation amplifier.
This signal would not be characteristic of this pressure sensing,
however, this example is used to illustrate the influence of
devices in the analog signal path.
The performance of this circuit with the above conditions is
shown in the FFT plot in Figure 5. It should be noticed that the
fundamental seems to be distorted and there are numerous
harmonics with the same distortion. The distortion is caused by
overdriving the amplifier slightly into the rails. The solution to this
problem is to lower the amplifier gain.
Figure 3: Once the power supply noise has been sufficiently
reduced, the output code of the MCP3201 is consistently one
code, 2108
Interfering External Clocks
Another source of systematic noise can come from clock sources
or digital switching in the circuit. If this type of noise is correlated
with the conversion process, it won’t appear as interference
in the conversion process. However, if it is uncorrelated, it can
easily be found with an FFT analysis.
An example of clocking signal interference is shown in the FFT
plot in Figure 4. With this plot, the circuit shown in Figure 1 is
used with the by-pass capacitors installed. The spurs seen in the Figure 5: Slightly overdriving an amplifier can generate a distortion
FFT plot shown in Figure 4 are generated by a 19.84 MHz clock in the signal. The FFT plot of this type of conversion quickly points
signal on the board. In this instance, layout has been done with out that the signal is distorted.
little regard for trace to trace coupling. The negligence to this
detail appears in the FFT plot.
Conclusion
This problem can be solved by changing the layout to keep high
Solving signal integrity problems can take a great deal of time
impedance analog traces away from digital switching traces or
particularly if you don’t have the tools to tackle the tough issues.
implementing an anti-aliasing filter in the analog signal path
The three best analysis tools to have in your “box of tricks” are
prior to the A/D converter. Random trace to trace coupling is
the frequency analysis (FFT), time analysis (scope photo) and
somewhat more difficult to find. In these instances, time domain
DC analysis (Histogram) tools. We used many of these tools
analysis can be more productive.
to identify the power supply noise, external clock noise and
overdriven amplifier distortion.
Figure 4: Digital noise coupled into analog traces is sometimes
misunderstood as broadband noise. An FFT plot easily pulls out
this so called “noise” into an identifiable frequency so the source
can be identified.
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An Intuitive Approach to Mixed Signal Layout – Part 6
Layout Tricks For A 12-Bit Sensing System
One Major Step Towards Disaster
When I started writing this article I thought a “cookbook”
approach would be appropriate when describing the
As I look at this complete circuit diagram I am tempted to use an
implementation of a good 12-bit layout. My assumption behind
auto router tool in my layout software. This is my first mistake. I
this type of approach is that a reference design could be
have found that when I use this type of tool I often will go back
provided, which would make the layout implementation easy. But
and make significant changes to the layout. If the tool is capable
I struggled with this topic long enough to find that this notion was
of implementing layout restrictions, I may have a fighting chance.
fairly unrealistic.
If my auto-routing tool does not have a restriction option, the best
Because of the complexity of this problem, I am going to approach is to not use it at all.
provide basic guidelines ending with a review of issues to be
General Layout Guidelines
aware of while implementing your layout design. Throughout
this discussion I will offer examples of good and bad layout Device Placement
implementations. I am doing this in the spirit of discussing
Now that I am working on this layout manually, my first step
concepts and not with the intent of recommending one layout as
is to place the devices on the board. This critical step is done
the only one to use.
effectively because I am keeping track of my noise-sensitive
The application circuit that I’m going to use is a load cell circuit devices and noise-creator devices. There are two guidelines that I
that accurately measures the weight applied to the sensor, use to accomplish this task:
then displays the results on an LCD display screen. The circuit
1. Separate the circuit devices into two categories: high speed
diagram for this system is shown in Figure 1. The load cell that
(>40 MHz) and low speed. When you can, place the higher
I used can be purchased from Omega (LCL-816G). My sensor
speed devices closer to the board connector/power supply.
model for the LCL-816G is a four element resistive bridge
2. Separate the above categories into three subcategories: pure
that requires voltage excitation. With a 5V excitation voltage
digital, pure analog and mixed signal. With this delineation,
applied to the high side of the sensor, the full scale output
place the digital devices closer to the board connector/power
swing is a ±10 mV differential signal with a 32 ounce maximum
supply.
excitation. This small differential signal is gained by a two-op
amp instrumentation amplifier. I chose a 12-bit converter to The board layout strategy should map the diagram shown in
match the required precision of this circuit. Once the converter Figure 2. Notice Figure 2a, the relationship of high speed versus
digitizes the voltage presented at its input, the digital code is slower speeds to the board connector/power supply. In Figure 2b,
sent to a microcontroller using the converter’s SPI™ port. The the digital and analog circuit is shown as being separate from the
microcontroller then uses a look-up table to convert the digital digital devices, which are closest to the board connector/power
signal from the ADC into weight. Linearization and calibration supply. The pure analog devices are furthest away from the digital
activities can be implemented with controller code at this point devices to insure that switching noise is not coupled into the
if need be. Once this is done the results are sent to the LCD analog signal path. The layout treatment of the A/D converters
display. As a final step, I wrote the firmware for the controller. is discussed in detail in part 4 of this 6-part series (Layout
Now the design is ready to go to board layout. Techniques To Use As The ADC Accuracy And Resolution Increase).
Figure 1: The signal at the output of the load-cell sensor is gained by a two-op amp instrumentation amplifier, filtered and digitized with a
12-bit A/D Converter, MCP3201. The result of each conversion is displayed on the LCD display
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An Intuitive Approach to Mixed Signal Layout – Part 6
a) High Frequency Components b) Digital Devices Should
Should Be Placed Near The Be Placed Near The
Connector/Power Source Connector/Power Source
high
frequency
low
Figure 2: The placement of active components on a PCB is critical in precision 12-bit+ circuits. This is done by placing higher frequency
components (a) closer to the connector and digital devices (b) closer to the connector.
Does my “no ground plane is required” theory play out? The proof
Ground and Power Supply Strategy
is in the pudding, or data. In Figure 4, 4096 samples were taken
Once I determine the general location of the devices, my ground
from the A/D converter and logged. No excitation is applied to
planes and power planes are defined. My strategy of the
the sensor when this data is taken. With this circuit layout, the
implementation of these planes is a bit tricky.
controller is dedicated to inter facing with the converter and
First of all, it is dangerous for me not to use a ground plane in sending the converter’s results to the LCD display.
a PCB implementation. This is true particularly in analog and/or
Figure 5 shows the same device layout shown in Figure 3
mixed-signal designs. One issue is that ground noise problems
but a ground plane on the bottom layer is added. The ground
are more difficult to deal with than power supply noise problems
plane (Figure 5b) has a few breaks due to signal. These breaks
because analog signals are referenced to ground. For instance, in
should be kept to a minimum. Current return paths should not
the circuit shown in Figure 1, the A/D converter’s inverting input
be “pinched” as a consequence of these traces restricting the
pin (MCP3201) is connected to ground. Secondly, the ground
easy flow of current from the device to the power connector.
plane also serves as a shield against emitted noise. Both of
The histogram for the A/D converter output is shown in Figure
these problems are easy to resolve with a ground plane and
6. Compared to Figure 4, the output codes are much tighter.
nearly impossible to overcome if there is no ground plane.
The same active devices were used for both tests. The passive
However, with my small design, I assume that I won’t need a devices were different causing a slight offset difference.
ground plane. A ground plane-less layout implementation of the
circuit in Figure 1 is shown in Figure 3.
Figure 3: Layout of the top (a) and bottom (b) layers of the circuit in Figure 1. Note that this layout does not have a ground or power plane.
Note that the power traces are made considerably wider than the signal traces in order to reduce power supply trace inductance.
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An Intuitive Approach to Mixed Signal Layout – Part 6
The inclusion of a power plane in a 12-bit system is not as
critical as the required ground plane. Although a power plane can
solve many problems, power noise can be reduced by making the
power traces two or three times wider than other traces on the
board and by using by-pass capacitors effectively.
Signal Traces
My signal traces on the board (both digital and analog) should
be as short as possible. This basic guideline will minimize the
opportunities for extraneous signals to couple into the signal
path. One area to be particularly cautious of is with the input
terminals of analog devices. These terminals normally have a
higher impedance than the output or power supply pins. As an
example, the voltage reference input pin to the A/D converter is
most sensitive while a conversion is occurring. With the type of
12-bit converter I have in Figure 1, my input terminals (IN+ and
IN-) are also sensitive to injected noise. Another potential for
noise injection into my signal path is the input terminals of an
Figure 4: This is a histogram of 4096 samples from the output
operational amplifier. These terminals have typically 109 to
of the A/D converter from a PCB that does not have a ground or
1013Ω input impedance.
power plane as shown in the PCB layout in Figure 3. The code of
My high impedance input terminals are sensitive to injected
the noise from the circuit is 15 codes wide.
currents. This can occur if the trace from a high impedance input
It is clear from my data that a ground plane does have an effect is next to a trace that has fast changing voltages, such as a
on the circuit noise. When my circuit did not have a ground plane, digital or clock signal. When a high impedance trace is in close
the width of the noise was ~15 codes. When I added a ground proximity to a trace with these types of voltage changes, charge
plane, I improved the performance by almost 1.5X or 15/11. It is capacitively coupled into the high impedance trace.
should be noted that my test set up was in the lab where EMI The relationship between two traces is shown in Figure 7. In
interference is relatively low. this diagram the value of the capacitance between two traces
Because of the noise shown with the A/D converter my digital is primarily dependent on the distance (d) between the traces
code is assignable to the op-amp noise and the absence of an and the distance that the two traces are in parallel (L). From this
anti-aliasing filter. If my circuit has a “minimum” amount of digital model, the amount of current generated into the high impedance
circuitry on board, a single ground plane and a single power plane trace is equal to:
may be appropriate. My qualifier “minimum” is defined by the
I = C dV/dt
board designer. The danger of connecting the digital and analog
Where: I = current that appears on the high impedance trace
ground planes together is that my analog circuitry can pick-up
the noise on the supply pins and couple it into the signal path. C= value of capacitance between the two PCB traces
In either case, my analog and digital grounds and power supplies dV = change in voltage of the trace that is switching
should be connected together at one or more points in the circuit dt = amount of time that the voltage change took to
to insure that my power supply, input and output ratings of all of get from one level to the next
the devices are not violated.
Figure 5: Layout of the top and bottom layers of the circuit in Figure 1. Note that this layout DOES have a ground plane.
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An Intuitive Approach to Mixed Signal Layout – Part 6
Every active device on the board requires a by-pass capacitor. It
must be placed as close as possible to the power supply pin of
the device as shown in Figure 5. If two by-pass capacitors are
used for one device, the smaller one should be closest to the
device pin. Finally, the lead length of the by-pass capacitor should
be as short as possible.
Anti-Aliasing Filters
You will note that the circuit in Figure 1 does not have an anti-
aliasing filter. As the data shows, this oversight has caused
noise problems in the circuit. When this board has a 4th order,
10 Hz, anti-aliasing filter inserted between the output of the
instrumentation amplifier and the input of the A/D converter,
the conversion response improves dramatically. This is shown in
Figure 8.
Analog filtering can remove noise superimposed on the analog
signal before it reaches the A/D converter. In particular, this
includes extraneous noise peaks. Analog-to-Digital converters will
Figure 6: This is a histogram of 4096 samples from the output of
convert the signal that is present on its input. This signal could
the A/D converter on the PCB that has a ground plane as shown in
include that sensor voltage signal or noise. The anti-aliasing filter
the PCB layout in Figure 5. The code width of the noise is now 11
removes the higher frequency noise from the conversion process.
codes wide.
Did I Say By-pass And Use An Anti-Aliasing Filter?
Although this article is about layout practices, I thought it would
be a good idea to cover some of the basics in circuit design.
A good rule concerning by-pass capacitors is to always include
them in the circuit. If they are not included the power supply
noise may very well eliminate any chance for 12-bit precision.
By-pass Capacitors
By-pass capacitors belong in two locations on the board: one at
the power supply (10 μF to 100 μF or both) and one for every
active device (digital and analog). The value of the device’s
by-pass capacitor is dependent on the device in question. If the
bandwidth of the device is less than or equal to ~1 MHz, a 1 μF
will reduce injected noise dramatically. If the bandwidth of the
device is above ~10 MHz, a 0.1 μF capacitor is probably
appropriate. In between these two frequencies, both or either
one could be used. Refer to the manufacturer’s guidelines for Figure 8: This diagram shows the conversion results of the circuit
specifics. in Figure 1 plus a 4th order, anti-aliasing filter. Additionally, the
board layout includes a ground plane.
PCB Design Check List
Good 12-bit layout techniques are not difficult to master as long
as you follow a few guidelines:
1. Check device placement versus connectors. Make sure that
high-speed devices and digital devices are closest to the
connector.
2. Always have at least one ground plane in the circuit.
3. Make power traces wider than other traces on the board.
4. Review current return paths and look for possible noise
sources on ground connects. This is done by determining the
current density at all points of the ground plane and the
amount of possible noise present.
5. By-pass all devices properly. Place the capacitors as close to
the power pins of the device as possible.
6. Keep all traces as short as possible.
7. Follow all high impedance traces looking for possible
capacitive coupling problems from trace to trace.
8. Make sure your signals in a mixed-signal circuit are properly
Figure 7: A capacitor can be constructed on a PCB by placing two
filtered.
traces in close proximity. With this PCB capacitor, signals can be
coupled between the traces.
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